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mmio_debuguse_mmio_flipenable_cmd_parserdisable_vtd_wadisable_displayinvert_brightnessprefault_disablefastbootenable_ipsdisable_power_wellpreliminary_hw_supportenable_psrenable_execlistsenable_ppgttenable_hangcheckresetvbt_sdvo_panel_typelvds_use_ssclvds_channel_modelvds_downclockenable_fbcenable_rc6semaphorespowersavepanel_ignore_lidmodesetgt_max_freq_mhz_storeerror_state_writegen6_enable_rpsvalleyview_enable_rpscherryview_enable_rpssandybridge_pcode_writesandybridge_pcode_readintel_get_cxsr_latencysnb_wm_latency_quirkintel_print_wm_latencyi915_ironlake_get_mem_freqgen7_enable_fbcironlake_disable_fbcironlake_enable_fbcg4x_enable_fbcg4x_disable_fbci8xx_enable_fbci8xx_disable_fbcskl_wm_flush_pipeilk_validate_wm_levelgen6_check_mch_setupcherryview_update_wmvalleyview_update_wmpineview_update_wmg4x_check_srwmg4x_update_wmi965_update_wmi9xx_update_wmi9xx_get_fifo_sizeintel_calculate_wmi845_update_wmi845_get_fifo_sizei830_get_fifo_sizeintel_init_pmintel_print_rc6_infointel_alloc_context_pageironlake_enable_drpsvalleyview_setup_pctxvalleyview_init_gt_powersavecherryview_setup_pctxcherryview_init_gt_powersavesanitize_rc6_optionwqke                        5  /  ) #|vp jd|^vXpRjLdF^@X:  R4!!L.""F(##@"$$: % %4!&!&."'"'(# (#("$)$)%)%{*&*&u+'+'o, (,(i-)-)c.).{*]/*/u+W0+0o,Q1,1i-K2-2c.E3.3]/?4/4W09505Q13616K2-727E3'838?4!94995:5:36;6;-7<7<'8 =8=!9>9>:>:ironlake_set_drpsQQRintel_set_memory_cxsrintel_update_fbcintel_cancel_fbc_work5-o*&_ &hb5k*k \_?  ? _?@?@@@@@@ @??@@?@@?@ @? @ 6 f  J   C D   >ލH x, \5 : j&V/ 5e M}s ̄ f jmƐ ae n  R 1a  K {5 L|+[  Fv0 :d W s Aq^Q n<l υ ܂  ς֎ ʌvlv_cmnlane_wahsw_set_power_wellintel_display_power_putintel_display_power_geti915_max_freq_seti915_min_freq_seti915_cache_sharing_seti915_ring_stop_seti915_ring_test_irq_seti915_drop_caches_seti915_error_state_writepipe_crc_set_sourcedisplay_crc_ctl_tokenizedisplay_crc_ctl_parsedisplay_crc_ctl_writecheck_cmdvmap_batchi915_parse_cmdsgen7_render_get_cmd_length_maskgen7_bsd_get_cmd_length_maskgen7_blt_get_cmd_length_maskP@P@hhh "### ##### #$#(#,#0#4#8#<#@#D#H#L#P#T#`#$$$ $ $0$4$8$<$@$RRR RRRRR@RDRHRLRPRTRXR\RRRRR $       ? ? @?? P?P?@?? @@?? @h ? ?9x:xCxDxExFxGx   ?@@?@ hipqqyz ! @@i915_gem_context_destroy_ioctli915_gem_context_create_ioctldo_switchi915_gem_create_contexti915_gem_context_initi915_gem_execbuffer2i915_gem_execbuffer_relocate_entryeb_lookup_vmasi915_gem_validate_contexti915_gem_do_execbufferi915_gem_execbufferi915_reset_gen7_sol_offsetsi915_gem_ringbuffer_submissionsanitize_enable_ppgtti915_gem_gtt_initi915_gem_setup_global_gtti915_check_and_clear_faultsgen8_ppgtt_initgen6_ppgtt_allocate_page_directoriesgen6_ppgtt_initi915_gem_openi915_gem_initi915_gem_unpin_ioctli915_gem_pin_ioctli915_gem_object_bind_to_vmi915_gem_object_set_cache_leveli915_context_is_bannedi915_gem_object_get_pagesi915_gem_mmap_gtti915_gem_object_create_stolen_for_preallocatedi915_pages_create_for_stoleni915_gem_object_create_stoleni915_stolen_to_physicali915_gem_init_stoleni915_setup_compressionABCi915_capture_error_state@intel_hpd_irq_eventi915_hotplug_work_funci915_error_work_funcivybridge_parity_workintel_hpd_irq_reenable_workgm45_get_vblank_counteri915_get_vblank_counteri915_get_vblank_timestampi915_get_crtc_scanoutposgen6_rps_irq_handleribx_irq_handlercpt_irq_handlersnb_gt_irq_handleri8xx_irq_handleri915_irq_handlerdisplay_pipe_crc_irq_handlerintel_hpd_irq_handleri965_irq_handler@``  @@"dev=%u, ring=%u, ctx=%p, ctx_vm=%p", REC->dev, REC->ring, REC->to, REC->vm"dev=%u, ctx=%p, ctx_vm=%p", REC->dev, REC->ctx, REC->vm"dev=%u, vm=%p", REC->dev, REC->vm"new_freq=%u", REC->freq"%s reg=0x%x, len=%d, val=(0x%x, 0x%x)", REC->write ? "write" : "read", REC->reg, REC->len, (u32)(REC->val & 0xffffffff), (u32)(REC->val >> 32)"plane=%d, obj=%p", REC->plane, REC->obj"plane=%d, obj=%p", REC->plane, REC->obj"dev=%u, ring=%u", REC->dev, REC->ring"dev=%u, ring=%u, seqno=%u, blocking=%s", REC->dev, REC->ring, REC->seqno, REC->blocking ? "yes (NB)" : "no""dev=%u, ring=%u, seqno=%u", REC->dev, REC->ring, REC->seqno"dev=%u, ring=%u, seqno=%u", REC->dev, REC->ring, REC->seqno"dev=%u, ring=%x, invalidate=%04x, flush=%04x", REC->dev, REC->ring, REC->invalidate, REC->flush"dev=%u, ring=%u, seqno=%u, flags=%x", REC->dev, REC->ring, REC->seqno, REC->flags"dev=%u, sync-from=%u, sync-to=%u, seqno=%u", REC->dev, REC->sync_from, REC->sync_to, REC->seqno"dev=%d, vm=%p", REC->dev, REC->vm"dev=%d", REC->dev"dev=%d, size=%d, align=%d %s", REC->dev, REC->size, REC->align, REC->flags & 0x1 ? ", mappable" : """obj=%p", REC->obj"obj=%p, %s index=%u %s", REC->obj, REC->gtt ? "GTT" : "CPU", REC->index, REC->write ? ", writable" : """obj=%p, offset=%u, len=%u", REC->obj, REC->offset, REC->len"obj=%p, offset=%u, len=%u", REC->obj, REC->offset, REC->len"obj=%p, read=%02x=>%02x, write=%02x=>%02x", REC->obj, REC->read_domains >> 16, REC->read_domains & 0xffff, REC->write_domain >> 16, REC->write_domain & 0xffff"obj=%p, offset=%08x size=%x vm=%p", REC->obj, REC->offset, REC->size, REC->vm"obj=%p, offset=%08x size=%x%s vm=%p", REC->obj, REC->offset, REC->size, REC->flags & 0x1 ? ", mappable" : "", REC->vm"obj=%p, size=%u", REC->obj, REC->size"pipe %c, frame=%u, scanline=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline"pipe %c, frame=%u, scanline=%u, min=%u, max=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline, REC->min, REC->max"pipe %c, frame=%u, scanline=%u, min=%u, max=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline, REC->min, REC->maxpopulate_lr_contextintel_lr_context_deferred_creategen8_init_common_ringintel_execlists_submission@ABCAinit_status_pageintel_ring_workarounds_emitinit_ring_commonintel_init_pipe_control0 0 00 xp  0 0 00 i yxaax x xxxxxxyyyxAxx@ xN x""3"xx HH @Z`w@ @Z`w` Z`w @Z`w a `" 1!  `@ `` ` ` ` @` ``!` !1$@~~~~~~~~0$  y1 $,ia yxy0x@1x2x3xxxxxxx!xx x xxx$x@#x`/x x@ x( x""##x`@*x`y{1  yZw .@Zw`.@1!  .`...@1  zix xxx QxxxxxxxPxx xRx0x@1x2x3xyyyyyyyy x x x x xIxJxKxyyy y@y`aayxyy@yyy yxxxy xyyy y xx@@@@ @@@@@ @$@(@,@0@4@8@<@@@D@H@L@P@T@X@\@`@d@h@l@p@t@x@|@C x"" h&x'x(x)x*xx $xOxMx@+x,x-x.x/xx#x`!x{????zix xxx Qxxxxx xxPxx xRx0x@1x2x3xyyyyyyyy x x x x xIxJxKxyyy y@y`aayxyy@yyy yxxxy xyyy y xx@@@@ @@@@@ @$@(@,@0@4@8@<@@@D@H@L@P@T@X@\@`@d@h@l@p@t@x@|@C x""Ux hx$xAOxMx@+x,x-x.x/xx#x!x&x'x(x)x*x{????g4x_audio_codec_enableg4x_audio_codec_disableilk_audio_codec_enableilk_audio_codec_disableaudio_config_hdmi_pixel_clockhsw_audio_codec_enablehsw_audio_codec_disableintel_audio_codec_enableWbpbxii&! "CD parse_ddi_portparse_mipiparse_edpparse_driver_featuresparse_device_mappingparse_sdvo_device_mappingparse_sdvo_panel_dataparse_lfp_backlightparse_lfp_panel_dataparse_general_definitionsparse_general_featuresvalidate_vbtinit_vbt_defaultsintel_no_opregion_vbt_callbackLENOVO97027RGintel_sanitize_crtcintel_sanitize_encoderintel_modeset_readout_hw_stateintel_modeset_setup_hw_statei915_redisable_vga_power_onintel_alloc_plane_objintel_setup_outputsintel_check_cursor_planeintel_crtc_cursor_set_objintel_prepare_primary_planedisable_crtc_nofbintel_modeset_stage_output_stateintel_set_config_compute_mode_changesintel_crtc_set_configintel_crtc_page_flipintel_crtc_initironlake_get_plane_configlpt_program_iclkipskylake_update_primary_planeironlake_update_primary_planeironlake_get_refclkironlake_crtc_compute_clockintel_enable_shared_dpllcpt_enable_fdi_bc_bifurcationintel_prepare_shared_dpllintel_disable_shared_dplli9xx_get_plane_configi9xx_pfit_disablei9xx_update_primary_planei9xx_set_pipeconfironlake_fdi_link_traingen6_fdi_link_trainivb_manual_fdi_link_trainivb_modeset_global_resourcesintel_modeset_initvlv_update_cdclkcheck_shared_dpll_statecheck_crtc_statecheck_encoder_stateintel_connector_check_stateintel_decrease_pllclocki9xx_crtc_clock_getintel_release_load_detect_pipeintel_dump_crtc_timingsintel_dump_pipe_configironlake_check_fdi_lanesironlake_fdi_compute_configconnected_sink_compute_bppcompute_baseline_pipe_bppintel_modeset_pipe_configintel_modeset_affected_pipesintel_get_load_detect_pipeintel_user_framebuffer_create_handleintel_framebuffer_inithsw_disable_pc8hsw_enable_pc8ironlake_init_pch_refclki9xx_get_refclkintel_get_shared_dpllNCR Corporation@H2)`(J;f+Hp =[ a0W5O~  *na0W5O~  pna0W5O  8na0W5Ov  pna0W5O  Pn  Ng5p Ng5P@  8kg5h * N8g5h pUg5h P ag5h  N\*Fxb N\*FxP@  a0W @`a0W @`!a0W @`!AR24C8 RG16XR24AR24XB24AB24XR30AR30XB30AB30C8 RG16XR24AR24XR15AR15intel_increase_pllclockintel_overlay_attrsintel_overlay_continueintel_overlay_put_image0`., h@+@ )`(`>(<9@7 64h`3న@2@1`00000 0@0@/00 .0, 0`+ 0 *` 0ീ( 0@? 0x<`@0 : @008@0x6 0@4` 0@2@ 0@`1 00intel_psr_match_conditionsintel_psr_enablevlv_sideband_rwintel_check_sprite_planeintel_dsm_platform_mux_infointel_dsm_pci_probeintel_dsm_detects~ONT,swsci_setupasle_isct_stateasle_set_dockingasle_set_convertibleasle_set_button_arrayasle_set_supported_rotation_anglesasle_set_pwm_freqasle_set_pfitasle_set_backlightasle_set_als_illumasle_workintel_opregion_setupintel_didl_outputsswsciintel_fbdev_restore_modeintel_fbdev_init_biosintelfb_createintel_fb_initial_configch7017_initch7017_mode_setch7017_dump_regsch7xxx_initch7xxx_writebch7xxx_readbch7xxx_dump_regsivch_initivch_writeivch_readivch_dump_regsns2501_initns2501_dpmsns2501_mode_validns2501_writebns2501_mode_setns2501_readb T= $%((  "#$%pO~&'0A ds'A#%(( 0Ⱥ   "#$%@2~&'0A T= $%((  "#$%pO~&'4Asil164_initsil164_writebsil164_readbsil164_dump_regstfp410_inittfp410_writebtfp410_readbtfp410_dump_regsintel_crt_resetintel_crt_load_detectintel_crt_detect_ddcvalleyview_crt_detect_hotplugintel_ironlake_crt_detect_hotplugintel_crt_detect_hotplugintel_crt_detectintel_crt_compute_confighsw_crt_post_disableintel_crt_get_edidACERZGBDell Inc.XPS 8700intel_ddi_initintel_ddi_get_configintel_ddi_pll_initintel_ddi_get_hw_statehsw_ddi_pll_selectskl_ddi_pll_selecthsw_fdi_link_train`@D@`HL``PT@`<0P@`@`@_  /ˀ_  _  _ _ ϲ oǀ_׀ o o  _  _  _  ___  _ À _׀ intel_dp_get_hw_stateintel_dp_get_configironlake_edp_pll_onironlake_set_pll_cpu_edpvlv_init_panel_power_sequencerintel_enable_dpintel_dp_link_downintel_dp_drrs_initintel_edp_backlight_powerintel_edp_init_connectorintel_dp_check_edpintel_dp_aux_chintel_dp_aux_initintel_dp_detect_dpcdintel_dp_detectintel_dp_set_propertyintel_dp_forceintel_dp_init_connectorintel_dp_set_drrs_state intel_dp_check_mst_statusintel_dp_probe_mstintel_dp_probe_ouiintel_dp_hpd_pulseintel_edp_panel_vdd_sanitizevlv_initial_power_sequencer_setupintel_dp_get_dpcdintel_dp_check_link_statusintel_dp_sink_crcintel_dp_complete_link_trainintel_gen6_edp_signal_levelsintel_gen7_edp_signal_levelsintel_hsw_signal_levelsintel_dp_set_signal_levelsintel_dp_start_link_trainintel_dp_sink_dpmsintel_edp_backlight_offintel_edp_backlight_onwait_panel_offedp_panel_offwait_panel_onedp_panel_onvlv_power_sequencer_kickintel_dp_init_panel_power_sequencer_registersintel_dp_init_panel_power_sequenceredp_panel_vdd_off_syncvlv_detach_power_sequencervlv_steal_power_sequencervlv_power_sequencer_pipewait_panel_statuswait_panel_power_cycleedp_panel_vdd_onintel_dp_compute_config  Q      intel_mst_disable_dpintel_mst_post_disable_dpintel_mst_pre_enable_dpintel_mst_enable_dpintel_dp_destroy_mst_connectordsi_vc_send_longprint_statdsi_vc_send_shortintel_dsi_hot_plugintel_dsi_compute_configintel_dsi_prepareintel_dsi_pre_pll_enableintel_dsi_enableintel_dsi_device_readyintel_dsi_pre_enableintel_dsi_enable_nopintel_dsi_pre_disableintel_dsi_clear_device_readyintel_dsi_disableintel_dsi_post_disableintel_dsi_get_hw_stateintel_dsi_get_configintel_dsi_detectintel_dsi_destroyintel_dsi_get_modesintel_dsi_mode_validintel_dsi_initvlv_get_dsi_pclkvlv_disable_dsi_pllvlv_configure_dsi_pllvlv_enable_dsi_pllun7y^Wj5bq8G#generic_initmipi_exec_send_packetmipi_exec_gpiogeneric_exec_sequenceintel_dvo_detect`8`v`u `8`u@8intel_enable_hdmiintel_hdmi_detectintel_hdmi_forcehsw_infoframe_enablehsw_infoframe_data_regg4x_infoframe_enableg4x_infoframe_indexintel_hdmi_compute_configintel_gmbus_force_bitgmbus_xferPPPP P$Pintel_lvds_detectintel_lvds_set_propertyintel_lvds_compute_configintel_lvds_initApple Inc.MacBookPro6,2Apple Inc.MacBookPro8,2Apple Inc.MacBookPro9,1AppleMacmini1,1AppleMacmini2,1MSIA9830IMSDell Inc.Studio Hybrid 140gDell Inc.OptiPlex FX170AOpeni965GMx-IF AOpen i915GMx-F AOpen i915GMm-HFS AOpen i45GMx-IAO00001JWClientronU800ClientronE830ASUSTeK Computer INC.EB1007 ASUSTeK Computer INC. AT5NM10T-I Hewlett-Packard t5740 Hewlett-Packardhp t5745 Hewlett-Packardhp st5747 MICRO-STAR INTERNATIONAL CO., LTD MS-7469 Gigabyte Technology Co., Ltd. D525TUDSupermicroX7SPA-HFUJITSUESPRIMO Q900 Intel D410PT IntelD425KT IntelD510MO IntelD525MWTOSHIBATECRA A11intel_backlight_device_update_statusintel_panel_get_backlightintel_backlight_device_registerbdw_enable_backlightpch_enable_backlightvlv_enable_backlighti965_enable_backlightget_backlight_min_vbti9xx_enable_backlightintel_panel_setup_backlightintel_panel_enable_backlightintel_panel_disable_backlightintel_panel_actually_set_backlightintel_sdvo_lvds_initintel_sdvo_analog_initintel_sdvo_create_enhance_property_lvdsintel_sdvo_create_enhance_property_tvintel_sdvo_create_enhance_propertyintel_sdvo_tv_initintel_sdvo_detectintel_sdvo_connector_matches_edidintel_sdvo_get_ddc_modesintel_sdvo_get_lvds_modesintel_sdvo_get_tv_modesintel_sdvo_dvi_initintel_sdvo_output_setupintel_sdvo_get_capabilitiesintel_sdvo_read_byteintel_sdvo_compute_configintel_sdvo_write_infoframeintel_enable_sdvointel_sdvo_read_responseintel_sdvo_debug_writeintel_sdvo_write_cmdintel_sdvo_get_configintel_sdvo_init320x200@@A320x240@@A400x300@&,-LM640x350@B^_~640x400@J640x480@~X704x480@0` 704x576@0r @A`a720x350@?I0^_~720x400@R0720x480@b0720x540@m0<=720x576@xt0@A`a768x576@R{@`@A`a800x600@ !`XYxy832x624@@Apq920x766@C1024x768@C@` !1280x1024@T@` !  !'()*+,}zghijklUVWXYZ^_`[\]abcdefMNO{PQRSTmnopqtuvwxyintel_tv_detect_typeintel_tv_detectintel_tv_compute_configintel_tv_init XP8$ @D|YH" @k@Q$ @D|YH" @k 6$ @D|YH" @k@Q$ @D|YH" @k@AP @L_I"  lq\P @L_I   lqC$@JzY ,,P@[_ 00?@E`P,,q @EPP,,  @EPXkO   @E`Xk  n(E2-EYSM <2-3jd z= v2-3-@  <2-3jd z= q2-3-@ 2-EyOv2-E?S  2-L"V q2-LFZ" <2-3jd z= q2-3-@ 0@5 . .5@0`5.-4@0`@6.-4 0`6. -3 0`70/,30` 8P/,20`8/ , 20`9/+10` :/`+`1 `:+ 1 @;(*0 @`<8 *0 =8)@0@=H`)0@>H)@`@?X(`` (` (`0@5 . .5@0`5.-4@0`@6.-4 0`6. -3 0`70/,30` 8P/,20`8/ , 20`9/+10` :/`+`1 `:+ 1 @;(*0 @`<8 *0 =8)@0@=H`)0@>H)@`@?X(`` (` (`0@6,-@606-,50@7@-,@507-@,40@8.+@408 .+409@.@+30:`.+@3@0:.*3@0@;.@*2@0<.*@20<.)20@=/@)10= /)10>@/(@10@? /@(@11(/(10@6,-@606-,50@7@-,@507-@,40@8.+@408 .+409@.@+30:`.+@3@0:.*3@0@;.@*2@0<.*@20<.)20@=/@)10= /)10>@/(@10@? /@(@11(/(1i915_getparami915_setparamintel_alloc_mchbar_resourcei915_dump_device_info@dD@AdBdCd @DdEd@!FdGd@Hd Id@ Jd @ Kd @ Ld@ Md@NdOd Qd@Sd@Td(@UdVd@1Wd1XdYdZd0[d0\d @0]d @0^d(0_d @ 0`d@!0ad"0bd#0cd$0dd%ed&0fd 'gd,@(hd,)1id@@*kd+kd,1ld-0md.0nd@/0od@00pd10qd20rd30sdfailed to re-initialize GPU, declaring wedged! 6[drm] This hardware requires preliminary hardware support. See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support GT register access while GT waking disabled /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_drv.cWARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)))WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev))WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev))WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev))GEM idle failed, resume might fail DRM not initialized, aborting suspend. 6[drm] Simulated gpu hang, resetting stop_rings 6[drm] Reset not implemented, but ignoring error for simulated gpu hangs 5drm/i915: Resetting chip after gpu hang timeout waiting for GFX clock force-on (%08x) waiting for GT wells to go %s (%08x) WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask)timeout waiting for GT wells to go %s device lock contention, deffering suspend Runtime suspend failed, disabling it (%d) failed to set PCI D0 power state (%d) Resume prepare failed: %d,Continuing resume Runtime resume failed, disabling it (%d) /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_sysfs.cUser requested overclocking to %d RC6 residency sysfs setup failed RC6p residency sysfs setup failed l3 parity slice 1 setup failed error_state sysfs setup failed Enabling RC6 states: RC6 %s RC6p %s RC6pp %s FIFO entries required for mode: %ld Wrong MCH_SSKPD value: 0x%08x This can cause underruns. enabled FBC, pitch %d, yoff %d, plane %c Setting FIFO watermarks - A: %d /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_pm.cSR watermark: display plane %d, cursor %d display watermark is too large(%d/%ld), disabling cursor watermark is too large(%d/%ld), disabling Primary WM%d too large %u (max %u) Sprite WM%d too large %u (max %u) Cursor WM%d too large %u (max %u) Unknown FSB/MEM found, disable CxSR cancelling pending FBC enable WARN_ON(!mutex_is_locked(&dev->struct_mutex))failed to alloc power context, RC6 disabled failed to pin power context: %d failed to set-domain on power context: %d /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hfbc disabled per module param more than one pipe active, disabling compression mode incompatible with compression, disabling mode too large for compression, disabling plane not A, disabling compression framebuffer not tiled or fenced, disabling compression Rotation unsupported, disabling framebuffer too large, disabling compression disabling active FBC for update Failed to allocate FBC work structure unsupported config, disabling FBC FIFO watermarks - A: %d, B: %d Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d self-refresh entries: %d, wm: %d self-refresh watermark: display plane %d cursor %d Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, SR: plane=%d, cursor=%d %s WM%d latency %u (%u.%u usec) gpu busy, RCS change rejected WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock))WARN_ON(val > dev_priv->rps.max_freq_softlimit)WARN_ON(val < dev_priv->rps.min_freq_softlimit)fmax: %d, fmin: %d, fstart: %d failed to enable ironlake power savings stuck trying to change perf mode warning: pcode (read) mailbox access failed timeout waiting for pcode read (%d) to finish unknown memory frequency 0x%02x WM latency values increased to avoid potential underruns Failed to read display plane latency. Disable CxSR 6[drm] failed to find known CxSR latency (found ddr%s fsb freq %d, mem freq %d), disabling CxSR unexpected fall-through in intel_init_pm warning: pcode (write) mailbox access failed timeout waiting for pcode write (%d) to finish Adjusting RC6 mask to %d (requested %d, valid %d) BIOS didn't set up PCBR, fixing up RP1(Guar) GPU freq: %d MHz (%u) not enough stolen space for PCTX, disabling RP1(Guar Freq) GPU freq: %d MHz (%u) GT fifo had a previous error %x WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0)current GPU freq: %d MHz (%u) setting GPU freq to %d MHz (%u) WARN_ON(pctx_addr != dev_priv->mm.stolen_base + dev_priv->vlv_pctx->stolen->start)Failed to set the min frequency Overclocking supported. Max: %dMHz, Overclock max: %dMHz Couldn't check for BIOS workaround You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV) Couldn't fix incorrect rc6 voltage /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_runtime_pm.cWARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && state != PUNIT_PWRGT_PWR_GATE(power_well_id))WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe))Requesting to disable the power well timout setting power well state %08x (%08x) Display PHY %d is not power up Getting nosync-ref while suspended. WARN_ON(!power_domains->domain_use_count[domain])toggling display PHY side reset 6[drm] RC6 disabled, disabling runtime PM support 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x crtc_mask: 0x%08x, active: %d, on: %s 0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s bit6 swizzle for X-tiling = %s bit6 swizzle for Y-tiling = %s Enabled by kernel parameter: %s /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_debugfs.cBusy frontbuffer bits: 0x%03x Logical Ring Contexts are disabled Execlist status: 0x%08X, context: %u Read pointer: 0x%08X, write pointer 0x%08X Status buffer %d: 0x%08X, context: %u %pK: %s%s%s %8zdKiB %02x %02x %u %u %u%s%s%sgtt offset: %08lx, size: %08lx)fbcon size: %d x %d, depth %d, %d bpp, refcount %d, obj user size: %d x %d, depth %d, %d bpp, refcount %d, obj Fence %d, pin count = %d, object = Total %d objects, %zu bytes, %zu GTT size FBC unsupported on this chipset FBC actived, but currently disabled in hardwaredisabled per module param (default off)GPU freq (MHz) Effective CPU freq (MHz) Effective Ring freq (MHz) PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x Lowest (RPN) frequency: %dMHz Nominal (RP1) frequency: %dMHz Max non-overclocked (RP0) frequency: %dMHz Max overclocked frequency: %dMHz PUNIT_REG_GPU_FREQ_STS: 0x%08x efficient (RPe) frequency: %d MHz Master Interrupt Control: %08x Display Engine port interrupt mask: %08x Display Engine port interrupt identity: %08x Display Engine port interrupt enable: %08x Display Engine misc interrupt mask: %08x Display Engine misc interrupt identity: %08x Display Engine misc interrupt enable: %08x North Display Interrupt enable: %08x North Display Interrupt identity: %08x North Display Interrupt mask: %08x South Display Interrupt enable: %08x South Display Interrupt identity: %08x South Display Interrupt mask: %08x Graphics Interrupt enable: %08x Graphics Interrupt identity: %08x Graphics Interrupt mask: %08x Graphics Interrupt mask (%s): %08x %u [%u] objects, %zu [%zu] bytes in gtt %u [%u] active objects, %zu [%zu] bytes %u [%u] inactive objects, %zu [%zu] bytes %u unbound objects, %zu bytes %u purgeable objects, %zu bytes %u pinned mappable objects, %zu bytes %u fault mappable objects, %zu bytes %s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound) Masking interrupts on rings 0x%08llx Manually setting uncore sharing to %llu Manually setting min freq to %llu Manually setting max freq to %llu Manually setting wedged to %llu (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)%hu %hu %hu %hu %hu %hu %hu %huid %d:"%s" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x CRTC %d: pipe: %c, active=%s (size=%dx%d) fb: %d, pos: %dx%d, size: %dx%d encoder %d: type: %s, connectors: connector %d: type: %s, status: %s cursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s underrun reporting: cpu=%s pch=%s connector %d: type %s, status: %s physical dimensions: %dx%dmm Context on %s with no gem object Failed to get pages for context object [0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x No flip due on pipe %c (plane %c) Flip queued on pipe %c (plane %c) Flip pending (waiting for vsync) on pipe %c (plane %c) Flip queued on %s at seqno %u, next seqno %u [current breadcrumb %u], completed? %d Flip not associated with any ring Flip queued on frame %d, (was ready on frame %d), now %d Stall check waiting for page flip ioctl, Current scanout address 0x%08x New framebuffer address 0x%08lx Trying to capture CRC while pipe is off collecting CRCs for pipe %c, %s expected <%lu bytes into pipe crc control too many words, allowed <= %d tokenize failed, a command is %d words Render RC6 residency since boot: %u Media RC6 residency since boot: %u RC information inaccurate because somebody holds a forcewake reference RC6 "Locked to RPn" residency since boot: %u RC6+ residency since boot: %u RC6++ residency since boot: %u CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_drv.hCMD: Abnormal blt cmd length! 0x%08X CMD: Abnormal bsd cmd length! 0x%08X CMD: Abnormal rcs cmd length! 0x%08X CMD: cmd_parser_init with unknown ring: %d /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_cmd_parser.cCMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X Failed to get space for pages CMD: Unrecognized command: 0x%08X CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td CMD: Rejected command: 0x%08X CMD: Rejected master-only command: 0x%08X CMD: Rejected LRM to OACONTROL CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d) CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d) CMD: batch set OACONTROL but did not clear it CMD: Got to the end of the buffer w/o a BBE cmd! /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_gem_context.cWARN_ON(dev_priv->ring[RCS].default_context)Disabling HW Contexts; invalid size %d Failed to create default global context (error %ld) %s context support initialized WARN_ON(!dev_priv->ring[RCS].last_context)WARN_ON(dctx->legacy_hw_ctx.rcs_state->active)WARN_ON(i915.enable_execlists)WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_gem_render_state.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_drv.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/asm-generic/dma-mapping-common.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(!list_empty(&vma->exec_list))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_gem_evict.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(i915_gem_evict_vm(vm, false))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_ringbuffer.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && !i915_is_ggtt(vma->vm))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_gem_execbuffer.creloc with multiple write domains: obj %p target %d offset %d read %08x write %08xreloc with read/write non-GPU domains: obj %p target %d offset %d read %08x write %08xRelocation beyond object bounds: obj %p target %d offset %d size %d. Relocation not 4-byte aligned: obj %p target %d offset %d. Invalid object handle %d at index %d Object %p [handle %d, index %d] appears more than once in object list execbuf with unknown ring: %d execbuf with invalid ring: %d Context %u tried to submit while banned Attempting to use self-modifying batch buffer clip rectangles are only valid with the render ring clip rectangles are only valid on pre-gen5 UXA submitting garbage DR4, fixing up 0 cliprects but dirt in cliprects fields non-0 rel constants mode on non-RCS rel surface constants mode invalid on gen5+ execbuf with unknown constants: %d Failed to allocate exec list for %d buffers copy %d exec entries failed %d failed to copy %d exec entries back to user (%d) failed to copy %d exec entries back to user PDE #%d mismatch: Actual PDE: %x Expected PDE: %x /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_gem_gtt.cWARN_ON(ppgtt->pd_offset & 0x3f)WARN_ON(readq(>t_entries[i-1]) != gen8_pte_encode(addr, level, true))First entry = %d; Num entries = %d (max=%d) WARN_ON(gtt != vm->pte_encode(addr, level, true, flags))WARN_ON(pdpe >= GEN8_LEGACY_PDPS)6[drm] applying Ironlake quirks for intel_iommu Failed to map the gtt page table Forced to use aperture for PDEs Allocated pde space (%ldM) at GTT entry: %lx 6[drm] Pages will be wasted unless GTT size (%llu) is divisible by 1GB Allocated %d pages for page directories (%d wasted) Allocated %d pages for page tables (%lld wasted) WARN_ON(!list_empty(&ppgtt->base.active_list))WARN_ON(!list_empty(&ppgtt->base.inactive_list))Unexpected fault Addr: 0x%08lx Address space: %s Source ID: %d Type: %d reserving preallocated space: %lx + %zx WARN_ON(i915_gem_obj_ggtt_bound(obj))clearing unused GTT space: [%lx, %lx] /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/drm/drm_mm.h6[drm] Memory usable by graphics device = %zdM 6[drm] VT-d active for gfx access 6[drm] Disabling PPGTT because VT-d is on disabling PPGTT on pre-B3 step VLV /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_drv.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(i915_gem_object_needs_bit17_swizzle(obj))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_gem.ccontext hanging too fast, banning! gpu hanging too fast, banning! Timed out waiting for the gpu reset to complete /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_drv.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_ringbuffer.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hAttempting to obtain a purgeable object 6[drm] BLT not supported on this pre-production hardware; graphics performance will be degraded. WARN_ON(!ggtt_vma || dev_priv->fence_regs[obj->fence_reg].pin_count > ggtt_vma->pin_count)WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0)Not pinned by caller in i915_gem_pin_ioctl(): %d Failed to initialize GPU, declaring it wedged WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex))WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits))WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex))WARN_ON(new->frontbuffer_bits & frontbuffer_bits)WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)%s vma for this object not found. bogus fence setup with stride: 0x%x, tiling mode: %i object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned object 0x%08lx not 512K or pot-size 0x%08x aligned 3Unable to purge GPU memory due lock contention. 6Purging GPU memory, %lu bytes freed, %lu bytes still pinned. 3%lu and %lu bytes still available in the bound and unbound GPU page lists. Attempting to mmap a purgeable buffer /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/scatterlist.hWARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL))WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)bo is already pinned with incorrect alignment: offset=%lx, req.alignment=%x, req.map_and_fenceable=%d, obj->map_and_fenceable=%d Invalid object alignment requested %u Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable)Attempting to pin a purgeable buffer Already pinned in i915_gem_pin_ioctl(): %d WARN_ON(obj->frontbuffer_bits)can not change the cache level of pinned objects WARN_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU)WARN_ON(was_pin_display != is_pin_display(obj))WARN_ON(!obj->map_and_fenceable)unhandled error in i915_gem_fault: %i &dev_priv->gpu_error.reset_queue/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_gem_stolen.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_drv.h6[drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS. reserved %d bytes of contiguous stolen space for FBC 6drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this. 6[drm] DMAR active, disabling use of stolen memory GTT within stolen memory at 0x%llx-0x%llx Stolen memory adjusted to 0x%x-0x%x conflict detected with stolen region: [0x%08x - 0x%08x] found %zd bytes of stolen memory at %08lx WARN_ON(bios_reserved > dev_priv->gtt.stolen_size)creating stolen object: size=%x creating preallocated stolen object: stolen_offset=%x, gtt_offset=%x, size=%x failed to allocate stolen space failed to allocate stolen object failed to allocate stolen GTT space /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(size == 0 || stolen_offset & 4095 || size & 4095)Couldn't read from MCHBAR. Disabling tiling. /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_drv.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hFailed to allocate memory for bit 17 record /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_gem_userptr.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/scatterlist.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(obj->userptr.mm == NULL)WARN_ON(i915_gem_object_put_pages(obj))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_gpu_error.cActive process (on ring %s): %s [%d] SYNC_0: 0x%08x [last synced 0x%08x] SYNC_1: 0x%08x [last synced 0x%08x] SYNC_2: 0x%08x [last synced 0x%08x] %s (w/a) --- gtt_offset = 0x%08x seqno 0x%08x, emitted %ld, tail 0x%08x /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hout of memory, not capturing error state 6[drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace. 6[drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel 6[drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue. 6[drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it. 6[drm] GPU crash dump saved to /sys/class/drm/card%d/error /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_irq.cWARN_ON(!intel_irqs_enabled(dev_priv))WARN_ON(I915_READ(SDEIER) != 0)Interrupt register 0x%x is not zero: 0x%08x trying to get vblank count for disabled pipe %c trying to get scanoutpos for disabled pipe %c No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx WARN_ON(!dev_priv->l3_parity.which_slice)Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d. WARN_ON(dev_priv->l3_parity.which_slice)Command parser error, iir 0x%08x Command parser error, gt_iir 0x%08x Reenabling HPD on connector %s running encoder hotplug functions 6[drm] HPD interrupt storm detected on connector %s: switching from hotplug detection to polling Connector %s (pin %i) received hotplug event. WARN_ON(!mutex_is_locked(&dev->mode_config.mutex))[CONNECTOR:%d:%s] status updated from %s to %s hotplug event received, stat 0x%08x, dig 0x%08x Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled Received HPD interrupt on PIN %d - cnt: 0 HPD interrupt storm detected on PIN %d Received HPD interrupt on PIN %d - cnt: %d PCH audio power change on port %c WARN_ON(pm_iir & ~dev_priv->pm_rps_events)WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock))Command parser error, pm_iir 0x%08x PCH audio power change on port %d PCH transcoder audio interrupt PCH transcoder CRC done interrupt PCH transcoder CRC error interrupt The master control interrupt lied (GT0)! The master control interrupt lied (GT1)! The master control interrupt lied (PM)! The master control interrupt lied (GT3)! The master control interrupt lied (DE MISC)! The master control interrupt lied (DE PORT)! Fault errors on pipe %c : 0x%08xThe master control interrupt lied (DE PIPE)! The master control interrupt lied (SDE)! WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events)pipe %c: enable_mask=0x%x, status_mask=0x%x 3i915: render error detected, EIR: 0x%08x 3i915: INSTDONE_%d: 0x%08x 3i915: memory refresh error: Hangcheck timer elapsed... %s idle 6[drm] Fake missed irq on %s pipe %c, frame=%u, scanline=%u, min=%u, max=%u pipe %c, frame=%u, scanline=%u obj=%p, offset=%08x size=%x%s vm=%p obj=%p, offset=%08x size=%x vm=%p obj=%p, read=%02x=>%02x, write=%02x=>%02x dev=%u, sync-from=%u, sync-to=%u, seqno=%u dev=%u, ring=%u, seqno=%u, flags=%x dev=%u, ring=%x, invalidate=%04x, flush=%04x dev=%u, ring=%u, seqno=%u, blocking=%s %s reg=0x%x, len=%d, val=(0x%x, 0x%x) dev=%u, ring=%u, ctx=%p, ctx_vm=%p WARN_ON(lrca & 0xFFFFFFFF00000FFFULL)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_lrc.cWARN_ON(!intel_irqs_enabled(dev_priv))WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex))WARN_ON(req1 && req1->elsp_submitted)WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0))WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj))WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1))WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj))WARN_ON(i915.enable_ppgtt == -1)Lite Restored request removed from queue Preemption without Lite Restore More than two context complete events? failed to quiesce %s whilst cleaning up: %d %s :timed out trying to stop ring /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hMore than 2 already-submitted reqs queued non-0 rel constants mode on non-RCS rel surface constants mode invalid on gen5+ execbuf with unknown constants: %d clip rectangles are only valid on pre-gen5 UXA submitting garbage DR4, fixing up 0 cliprects but dirt in cliprects fields WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0)WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL)WARN_ON(INTEL_INFO(ring->dev)->gen < 8)Alloc LRC backing obj failed: %d Pin LRC backing obj failed: %d Failed to allocate ringbuffer %s Failed to allocate ringbuffer obj %s: %d Failed to pin and map ringbuffer %s: %d /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_drv.hWARN_ON(idx >= I915_MAX_WA_REGS)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_ringbuffer.cWARN_ON(!intel_irqs_enabled(dev_priv))timed out waiting for the BSD ring to wake up %s : timed out trying to stop ring /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hFailed to allocate seqno page %s pipe control offset: 0x%08x WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0)%s: wait for SyncFlush to complete for TLB invalidation timed out %s head not reset to zero ctl %08x head %08x tail %08x start %08x failed to set %s head to zero ctl %08x head %08x tail %08x start %08x %s initialization failed [head=%08x], fudging %s initialization failed ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx] Failed to allocate status page Failed to allocate ringbuffer %s: %d Failed to pin and map ringbuffer %s: %d WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID)Failed to allocate semaphore bo. Disabling semaphores Failed to pin semaphore bo. Disabling semaphores WARN_ON(!dev_priv->semaphore_obj)No dual-BSD ring on non-BDW machine Number of Workarounds emitted: %d failed to quiesce %s whilst cleaning up: %d WARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0)WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_uncore.cTimed out: Render forcewake old ack to clear. Timed out: waiting for Render to ack. Timed out: Media forcewake old ack to clear. Timed out: waiting for media to ack. Timed out: waiting for Media to ack. Timed out: Blitter forcewake old ack to clear. Timed out: waiting for Blitter to ack. WARN_ON(!dev_priv->uncore.forcewake_count)Unclaimed register detected %s %s register 0x%x Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem.GT thread status wait timed out Timed out waiting for forcewake old ack to clear. Timed out waiting for forcewake to ack request. WARN_ON(dev_priv->uncore.fw_rendercount == 0)WARN_ON(dev_priv->uncore.fw_mediacount == 0)WARN_ON(dev_priv->uncore.fw_blittercount == 0)WARN_ON(!dev_priv->uncore.fw_rendercount)WARN_ON(!dev_priv->uncore.fw_mediacount)WARN_ON(dev_priv->uncore.forcewake_count > 0)6[drm] No MT forcewake available on Ivybridge, this can result in issues 6[drm] when using vblank-synced partial screen updates. Unclaimed register before interrupt Disable audio codec on pipe %c Disable audio codec on port %c, pipe %c /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_audio.cWARN_ON(acomp->ops || acomp->dev)HDMI audio pixel clock setting for %d not found, falling back to defaults Configuring HDMI audio for pixel clock %d (0x%08x) Enable audio codec on pipe %c, %u bytes ELD Enable audio codec on port %c, pipe %c, %u bytes ELD Enable audio codec, %u bytes ELD ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s] failed to add audio component (%d) Falling back to manually reading VBT from VBIOS ROM for %s BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d BDB_GD too small (%d). Invalid. DRRS supported mode is static DRRS supported mode is seamless DRRS not supported (VBT input) Found panel mode in BIOS VBT tables: LVDS downclock is found in VBT. Normal Clock %dKHz, downclock %dKHz Unsupported backlight data entry size %u PWM backlight not present in VBT (type %u) VBT backlight PWM modulation frequency %u Hz, active %s, min brightness %u, level %u Ignore SDVO panel mode from BIOS VBT tables. Found SDVO panel mode in BIOS VBT tables: No general definition block is found, unable to construct sdvo mapping. different child size is found. Invalid. the SDVO device with slave addr %2x is found on %s port SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d Maybe one SDVO port is shared by two SDVO device. there exists the slave2_addr. Maybe this is a SDVO device with multiple inputs. No SDVO device info is found in VBT No general definition block is found, no devices defined. no child dev is parsed from VBT No memory space for child device No eDP BDB found but eDP panel supported. VBT has unknown eDP link rate value %u VBT has unknown eDP lane count value %u VBT has unknown eDP pre-emphasis value %u VBT has unknown eDP voltage swing value %u Found MIPI Config block, panel index = %d No MIPI Sequence found, parsing complete Unable to parse MIPI Sequence Block v3+ Sequence start is beyond sequence block size, corrupted sequence block Corrupted sequence/size, bailing out Sequence elements going beyond block itself. Sequence block parsing failed MIPI related vbt parsing complete More than one child device for port %c in VBT. Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d Internal DP port %c is TMDS compatible Analog port %c is also DP or TMDS compatible Port %c is not DP/TMDS/CRT compatible Unexpected DDC pin for port B Unexpected DDC pin for port C Unexpected DDC pin for port D Unexpected AUX channel for port A Unexpected AUX channel for port B Unexpected AUX channel for port C Unexpected AUX channel for port D VBT HDMI level shift for port %c: %d Sequence block detected but no valid configuration WARN_ON(clock->n == 0 || clock->p == 0)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_display.cWARN_ON(clock->n + 2 == 0 || clock->p == 0)plane %c assertion failure, should be disabled but not plane %c assertion failure, should be off on pipe %c but is still active plane %d assertion failure, should be off on pipe %c but is still active sprite %c assertion failure, should be off on pipe %c but is still active FDI RX state assertion failure (expected %s, current %s) FDI TX state assertion failure (expected %s, current %s) Current CD clock rate: %d kHz WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE)WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE)Invalid cursor width/stride, width=%u, stride=%u FDI_RX_IIR before link train 0x%x FDI train 1 fail on vswing %d FDI train 2 fail on vswing %d PCH refclk assertion failure, should be active but is disabled WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)))WARN_ON(!mutex_is_locked(&dev->struct_mutex))hardware does not support tiling Y pitch (%d) must be at least 64 byte aligned %s pitch (%d) must be at less than %d pitch (%d) must match tiling stride (%d) 6[drm] applying inverted panel brightness quirk 6[drm] Backlight polarity reversed on %s 6[drm] applying backlight present quirk 6[drm] applying lvds SSC disable quirk 6[drm] applying pipe b force quirk 6[drm] applying pipe a force quirk unknown plane in flip command unknown tiling in flip command Unknown pnv display core clock 0x%04x WARN_ON(drm_crtc_vblank_get(crtc) == 0)Writing base %08lX %d,%d,%d,%d pitch=%d WARN_ON(__i915_wait_seqno(ring, seqno, intel_crtc->reset_counter, false, NULL, NULL) != 0)failed to move cursor bo into the GTT failed to release fence for cursorCursor dimension not supported mismatch in cpu_transcoder (expected %i, found %i) mismatch in has_pch_encoder (expected %i, found %i) mismatch in fdi_lanes (expected %i, found %i) mismatch in fdi_m_n.gmch_m (expected %i, found %i) mismatch in fdi_m_n.gmch_n (expected %i, found %i) mismatch in fdi_m_n.link_m (expected %i, found %i) mismatch in fdi_m_n.link_n (expected %i, found %i) mismatch in fdi_m_n.tu (expected %i, found %i) mismatch in has_dp_encoder (expected %i, found %i) mismatch in dp_m_n.gmch_m (expected %i, found %i) mismatch in dp_m_n.gmch_n (expected %i, found %i) mismatch in dp_m_n.link_m (expected %i, found %i) mismatch in dp_m_n.link_n (expected %i, found %i) mismatch in dp_m_n.tu (expected %i, found %i) mismatch in dp_m2_n2.gmch_m (expected %i, found %i) mismatch in dp_m2_n2.gmch_n (expected %i, found %i) mismatch in dp_m2_n2.link_m (expected %i, found %i) mismatch in dp_m2_n2.link_n (expected %i, found %i) mismatch in dp_m2_n2.tu (expected %i, found %i) mismatch in dp_m_n.gmch_m (expected %i or %i, found %i) mismatch in dp_m_n.gmch_n (expected %i or %i, found %i) mismatch in dp_m_n.link_m (expected %i or %i, found %i) mismatch in dp_m_n.link_n (expected %i or %i, found %i) mismatch in dp_m_n.tu (expected %i or %i, found %i) mismatch in adjusted_mode.crtc_hdisplay (expected %i, found %i) mismatch in adjusted_mode.crtc_htotal (expected %i, found %i) mismatch in adjusted_mode.crtc_hblank_start (expected %i, found %i) mismatch in adjusted_mode.crtc_hblank_end (expected %i, found %i) mismatch in adjusted_mode.crtc_hsync_start (expected %i, found %i) mismatch in adjusted_mode.crtc_hsync_end (expected %i, found %i) mismatch in adjusted_mode.crtc_vdisplay (expected %i, found %i) mismatch in adjusted_mode.crtc_vtotal (expected %i, found %i) mismatch in adjusted_mode.crtc_vblank_start (expected %i, found %i) mismatch in adjusted_mode.crtc_vblank_end (expected %i, found %i) mismatch in adjusted_mode.crtc_vsync_start (expected %i, found %i) mismatch in adjusted_mode.crtc_vsync_end (expected %i, found %i) mismatch in pixel_multiplier (expected %i, found %i) mismatch in has_hdmi_sink (expected %i, found %i) mismatch in limited_color_range (expected %i, found %i) mismatch in has_infoframe (expected %i, found %i) mismatch in has_audio (expected %i, found %i) mismatch in adjusted_mode.flags(DRM_MODE_FLAG_INTERLACE) (expected %i, found %i) mismatch in adjusted_mode.flags(DRM_MODE_FLAG_PHSYNC) (expected %i, found %i) mismatch in adjusted_mode.flags(DRM_MODE_FLAG_NHSYNC) (expected %i, found %i) mismatch in adjusted_mode.flags(DRM_MODE_FLAG_PVSYNC) (expected %i, found %i) mismatch in adjusted_mode.flags(DRM_MODE_FLAG_NVSYNC) (expected %i, found %i) mismatch in pipe_src_w (expected %i, found %i) mismatch in pipe_src_h (expected %i, found %i) mismatch in gmch_pfit.control (expected %i, found %i) mismatch in gmch_pfit.pgm_ratios (expected %i, found %i) mismatch in gmch_pfit.lvds_border_bits (expected %i, found %i) mismatch in pch_pfit.enabled (expected %i, found %i) mismatch in pch_pfit.pos (expected %i, found %i) mismatch in pch_pfit.size (expected %i, found %i) mismatch in ips_enabled (expected %i, found %i) mismatch in double_wide (expected %i, found %i) mismatch in ddi_pll_sel (expected 0x%08x, found 0x%08x) mismatch in shared_dpll (expected %i, found %i) mismatch in dpll_hw_state.dpll (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.dpll_md (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.fp0 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.fp1 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.wrpll (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.ctrl1 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.cfgcr1 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.cfgcr2 (expected 0x%08x, found 0x%08x) mismatch in pipe_bpp (expected %i, found %i) mismatch in adjusted_mode.crtc_clock (expected %i, found %i) mismatch in port_clock (expected %i, found %i) PCH DP (0x%08x) enabled on transcoder %c, should be disabled IBX PCH dp port still using transcoder B PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled IBX PCH hdmi port still using transcoder B transcoder assertion failed, should be off on pipe %c but is still active WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe))unknown pipe linked to edp transcoder WARN_ON(!pll->get_hw_state(dev_priv, pll, &pipe_config->dpll_hw_state))Unknown DPLL mode %08x in programmed mode attempting to use a userptr for a framebuffer, denied [CRTC:%d]%s config for pipe %c fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u crtc timings: %d %d %d %d %d %d %d %d %d, type: 0x%x flags: 0x%x gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x pch pfit: pos: 0x%08x, size: 0x%08x, %s crtc's computed active state doesn't match tracked active state (expected %i, found %i) crtc's computed enabled state doesn't match tracked enabled state (expected %i, found %i) crtc active state doesn't match with hw state (expected %i, found %i) active crtc, but not enabled in sw tracking plane %c assertion failure (expected %s, current %s) cursor on pipe %c assertion failure (expected %s, current %s) DSI PLL state assertion failure (expected %s, current %s) FDI mPHY reset assert timeout FDI mPHY reset de-assert timeout /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_drv.hWARN_ON(!intel_fb->obj->framebuffer_references--)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq)timed out waiting for CDclk change more active pll users than references: %i vs %i pll on state mismatch (expected %i, found %i) pll active crtcs mismatch (expected %i, found %i) pll enabled crtcs mismatch (expected %i, found %i) pll in active use but not on in sw tracking pll in on but not on in use in sw tracking pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x using SSC reference clock of %d kHz Couldn't find PLL settings for mode! PLL state assertion failure (expected %s, current %s) asserting DPLL %s with no DPLL %s assertion failure (expected %s, current %s) WARN_ON(pll->config.crtc_mask == 0)disable %s (active %d, on? %d) for crtc %d enable %s (active %d, on? %d) for crtc %d FDI RX PLL assertion failure (expected %s, current %s) FDI TX PLL assertion failure, should be active but is disabled WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)))panel assertion failure, pipe %c regs locked WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT)failed to enable transcoder %c pipe %c assertion failure (expected %s, current %s) WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE)timed out waiting for port %c ready: 0x%08x Y tiled bo slipped through, driver bug! WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex))pipe is still busy with an old pageflip no plane for crtc: plane %c, num_pipes %d Writing base %08lX %08lX %d %d %d WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue))WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, !intel_crtc_has_pending_flip(crtc), 60*HZ) == 0)flip queue: previous flip completed, continuing flip queue: crtc already busy /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_ringbuffer.hWARN_ON(intel_fb_obj(old_fb) == NULL)CRTC:%d using pre-allocated %s WARN_ON(pll->new_config->crtc_mask)CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d) failed to find PLL for pipe %c WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000))Timed out waiting for IPS enable WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0))Timed out waiting for IPS disable disabling pfit, current: 0x%08x PCH VGA enabled on transcoder %c, should be disabled PCH LVDS enabled on transcoder %c, should be disabled failed to disable transcoder %c Failed to disable PCH transcoder WARN_ON(pll->new_config == &pll->config)WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base))WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config)WARN_ON(intel_crtc->new_config && intel_crtc->new_config != &intel_crtc->config)set mode pipe masks: modeset: %x, prepare: %x, disable: %x rejecting invalid cloning configuration rejecting conflicting digital port configuration WARN_ON(INTEL_INFO(dev)->gen > 3)WARN_ON(INTEL_INFO(dev)->gen < 4)[CONNECTOR:%d:%s] checking for sink bpp constrains clamping display bpp (was %d) to EDID reported max of %d clamping display bpp (was %d) to default limit of %d checking fdi config on pipe %c, lanes %i invalid fdi lane config on pipe %c: %i lanes only 2 lanes on haswell, required: %i lanes invalid shared fdi lane config on pipe %c: %i lanes fdi link B uses too many lanes to enable link C fdi link bw constraint, reducing pipe bpp to %i loop in pipe configuration computation CRTC bw constrained, retrying plane bpp: %i, pipe bpp: %i, dithering: %i WARN_ON(!pll->config.crtc_mask)mode set failed: pipe %c stuck WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & ~SBI_SSCDIVINTPHASE_DIVSEL_MASK)iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x Failed to enable PCH transcoder has_panel %d has_lvds %d has_ck505 %d D_COMP RCOMP still in progress Switching back to LCPLL failed Kicking stuck page flip: queued at %d, now %d active connector not linked to encoder encoder->connectors_active not set encoder active on the wrong pipe connector's staged encoder doesn't match current encoder encoder's stage crtc doesn't match current crtc encoder's enabled state mismatch (expected %i, found %i) encoder's computed active state doesn't match tracked active state (expected %i, found %i) encoder's hw state doesn't match sw tracking (expected %i, found %i) mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u)) mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u)) encoder's active_connectors set, but no crtc active encoder's pipe doesn't match(expected %i, found %i) [CONNECTOR:%d:%s], [ENCODER:%d:%s] no pipe available for load-detect creating tmp fb for load-detection reusing fbdev for load-detection framebuffer failed to allocate framebuffer for load-detection failed to set mode on load-detect pipe [CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i) WARN_ON(set->connectors == NULL)modes are different, full mode set computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d [CONNECTOR:%d:%s] to [NOCRTC] encoder changed, full mode switch [CONNECTOR:%d:%s] to [CRTC:%d] WARN_ON(!connector->new_encoder->new_crtc)crtc changed, full mode switch crtc %sabled, full mode switch failed to set mode on [CRTC:%d], err = %d Trying to restore without FB -> disabling pipe %c failed to restore config after modeset failure WARN_ON(!set->fb && (set->num_connectors != 0))WARN_ON(set->fb && (set->num_connectors == 0))FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex))Something enabled VGA plane, disabling it [CRTC:%d] hw state readout: %s %s hw state readout: crtc_mask 0x%08x, on %i [ENCODER:%d:%s] hw state readout: %s, pipe %c [CONNECTOR:%d:%s] hw state readout: %s [ENCODER:%d:%s] has active connectors but no active pipe! [ENCODER:%d:%s] manually disabled [CRTC:%d] wrong plane connection detected! [CRTC:%d] hw state adjusted, was %s, now %s WARN_ON(encoder->connectors_active)%s enabled but not in use, disabling SSC %sabled by BIOS, overriding VBT which says %sabled swapping pipes & planes for FBC WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe)pipe %c sprite %c init failed: %d failed to pin boot fb on pipe %d /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_fifo_underrun.cuncleared fifo underrun on pipe %c uncleared pch fifo underrun on pch transcoder %c PCH transcoder %c FIFO underrun WARN_ON(!mutex_is_locked(&dev->struct_mutex))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_frontbuffer.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_overlay.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE))buffer used for overlay image can not be tiled failed to attach phys overlay regs failed to pin overlay register bo failed to move overlay register bo into the GTT 6[drm] initialized overlay support Overlay, status: 0x%08x, interrupt: 0x%08x WARN_ON(!(val & EDP_PSR_ENABLE))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_psr.cWARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE)Timed out waiting for PSR Idle for re-enable PSR not supported on this platform PSR not supported by this panel WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex))WARN_ON(!drm_modeset_is_locked(&crtc->mutex))PSR condition failed: Stereo 3D is Enabled PSR condition failed: Interlaced is Enabled Timed out waiting for PSR Idle State WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_sideband.cIOSF sideband idle wait (%s) timed out IOSF sideband finish wait (%s) timed out WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock))DPIO read pipe %c reg 0x%x == 0x%x timeout waiting for SBI to become ready timeout waiting for SBI to complete read transaction timeout waiting for SBI to complete write transaction /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_sprite.cUnsuitable framebuffer for plane Horizontal scaling factor out of limits Vertical scaling factor out of limits WARN_ON(!intel_plane->can_scale)Source dimensions exceed hardware limits WARN_ON(src->x1 < (int) orig_src->x1 || src->y1 < (int) orig_src->y1 || src->x2 > (int) orig_src->x2 || src->y2 > (int) orig_src->y2)WARN_ON(!primary_enabled && !state->visible && intel_crtc->active)WARN_ON(drm_vblank_get(dev, pipe))Potential atomic update failure on pipe %c Atomic update failure on pipe %c (start=%u end=%u) no _DSM method for intel device VGA switcheroo: detected DSM switching method %s handle 6[drm] ACPI BIOS requests an excessive sleep of %u ms, using %u ms instead SWSCI request already in progress No request on ASLC interrupt 0x%08x opregion backlight request ignored updating opregion backlight %d/255 Button array event is not supported (nothing) Button array event is not supported (rotation lock) Button array event is not supported (volume down) Button array event is not supported (volume up) Button array event is not supported (windows) Button array event is not supported (power) Convertible is not supported (clamshell) Convertible is not supported (slate) Docking is not supported (docked) Docking is not supported (undocked) unsupported intel_encoder type %d /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_opregion.c4i915: No ACPI video bus found More than 8 outputs detected via ACPI More than 8 outputs in connector list graphic opregion physical addr: 0x%x Public ACPI methods supported SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x) SWSCI GBDA callbacks %08x, SBCB callbacks %08x connector %s not enabled, skipping connector %s is disabled by user, skipping /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_fbdev.cconnector %s has no encoder or crtc, skipping fallback: cloned configuration looking for cmdline mode on connector %s looking for preferred mode on connector %s %d using first mode listed on connector %s looking for current mode on connector %s connector %s on pipe %c [CRTC:%d]: %dx%d%s fallback: Not all outputs enabled Not using firmware configuration failed to allocate framebuffer /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hBIOS fb too small (%dx%d), we require (%dx%d), releasing it no BIOS fb, allocating a new one allocated %dx%d fb: 0x%08lx, bo %p WARN_ON(INTEL_INFO(dev)->num_pipes == 0)pipe %c not active or no fb, skipping found possible fb from plane %c no active fbs found, not using BIOS config checking plane %c for BIOS fb fb not wide enough for plane %c (%d vs %d) pipe %c area: %dx%d, bpp: %d, size: %d fb not big enough for plane %c (%d vs %d) fb big enough for plane %c (%d >= %d) BIOS fb not suitable for all pipes, not using re-used BIOS config but lost an fb on crtc %d using BIOS fb for initial console WARN_ON(state != FBINFO_STATE_RUNNING)CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT: %02x CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT: %02x CH7017_VERTICAL_ACTIVE_LINE_OUTPUT: %02x CH7017_ACTIVE_INPUT_LINE_OUTPUT: %02x CH7017_LVDS_PLL_VCO_CONTROL: %02x CH7017_LVDS_PLL_FEEDBACK_DIV: %02x Registers before mode setting ch701x not detected, got %d: from %s slave %d. Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. ch7xxx not detected; got 0x%02x from %s slave %d. Detected %s chipset, vendor/device ID 0x%02x/0x%02x Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. ivch detect failed due to address mismatch (%d vs %d) Unable to read register 0x%02x from %s:0x%02x. Unable to write register 0x%02x to %s:%d set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d). is mode valid (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d) Trying set the dpms of the DVO to %i WARN_ON(ns->regs[83].offset != 0x08 || ns->regs[84].offset != 0x41 || ns->regs[85].offset != 0xc0)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/dvo_ns2501.cns2501 not detected got %d: from %s Slave %d. init ns2501 dvo controller successfully! Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. sil164 not detected got %d: from %s Slave %d. init sil164 dvo controller successfully! Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. tfp410 not detected got VID %X: from %s Slave %d. tfp410 not detected got DID %X: from %s Slave %d. WARN_ON(!(val & SPLL_PLL_ENABLE))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_crt.c6[drm] Skipping CRT initialization for %s CRT GMBUS EDID read failed, retry using GPIO bit-banging CRT detected via DDC:0x50 [EDID] CRT not detected via DDC:0x50 [EDID reports a digital panel] CRT not detected via DDC:0x50 [no valid EDID found] trigger hotplug detect cycle: adpa=0x%x timed out waiting for FORCE_TRIGGERironlake hotplug adpa=0x%x, result %d valleyview hotplug adpa=0x%x, result %d timed out waiting for FORCE_DETECT to go offTimeout waiting for DDI BUF %c idle bit /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_ddi.c%d encoders on crtc for pipe %c pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp No pipe for ddi port %c found compute_config() on unknown output! WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE)ddi translation table missing WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL)FDI link training done on step %d No valid values found for the given pixel clock failed to find PLL for pipe %c Invalid encoder type %d for pipe %c VBT says port %c is not DVI/HDMI/DP compatible, assuming it is /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_dp.cWARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)DP training pattern 3 not supported dp port still on, should be off 160MHz cpu eDP clock, might need ilk devA w/a pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp No pipe for dp port 0x%x found VDD left on by BIOS, adjusting state tracking WARN_ON(intel_dp->want_panel_vdd)PP_STATUS: 0x%08x PP_CONTROL: 0x%08x detaching pipe %c power sequencer from port %c WARN_ON(pipe != PIPE_A && pipe != PIPE_B)stealing pipe %c power sequencer from port %c stealing pipe %c power sequencer from active eDP port %c picked pipe %c power sequencer for port %c skipping pipe %c power seqeuncer kick due to port %c being active kicking pipe %c power sequencer for port %c panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d panel power up delay %d, power down delay %d, power cycle delay %d backlight on delay %d, off delay %d no initial power sequencer for port %c initial power sequencer for port %c: pipe %c Broken DP branch device, ignoring mask %08x value %08x status %08x control %08x Panel status timeout: status %08x control %08x eDP port %c panel power wasn't enabled eDP powered off while attempting aux channel communication. WARN_ON(send_bytes > 20 || recv_size > 20)dp aux hw did not signal timeout (has irq: %i)! dp_aux_ch not done status 0x%08x dp_aux_ch receive error status 0x%08x dp_aux_ch timeout status 0x%08x dp_aux_ch not started status 0x%08x Turn eDP port %c panel power on eDP port %c panel power already on Unsupported voltage swing/pre-emphasis level:0x%x /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_drv.hpanel power control backlight %s invalid max DP link bw val %x, using 1.62Gbps DP link computation with max lane count %i max bw %02x pixel clock %iKHz clamping bpp for eDP panel to BIOS-provided %i DP link bw %02x lane count %d clock %d bpp %d DP link bw required %i available %i eDP port %c VDD already requested on Turn eDP port %c panel power off Need eDP port %c VDD to turn off panel Wait for panel power off time failed to %s sink power state failed to enable link training too many full retries, give up too many voltage retries, give up failed to update link training failed to start channel equalization Channel EQ done. DP Training successful Timed out waiting for DP idle patterns channel EQ not ok, retraining failed to get ESI - device may have failed initializing pipe %c power sequencer for port %c Panel is unable to calculate CRC after 6 vblanks WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex))WARN_ON(!intel_encoder->base.crtc)CP or sink specific irq unhandled %s: channel EQ not ok, retraining ignoring long hpd on eDP port %c MST device may have disappeared %d vs %d Refresh rate should be positive non-zero. DRRS is disabled as PSR is enabled DRRS: intel_crtc not initialized Only Seamless DRRS supported. DRRS requested for previously set RR...ignoring eDP encoder disabled. CRTC not Active eDP Refresh Rate set to : %dHz Adding %s connector on port %c drm_dp_aux_register() for %s failed (%d) sysfs_create_link() for %s failed (%d) 6[drm] failed to retrieve link info, disabling eDP DRRS supported for Gen7 and above seamless DRRS supported for eDP panel. using pipe %c for initial backlight setup WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) && port != PORT_B && port != PORT_C)Timed out waiting for ACT sent RXDSI_DATA_TYPE_NOT_REGOGNISED TXDSI_DATA_TYPE_NOT_RECOGNISEDchannel %d, data_type %d, data %04x MIPI_INTR_STAT(%d) = %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s Timeout waiting for HS/LP CTRL FIFO !full /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_dsi_cmd.cchannel %d, data_type %d, len %04x Timeout waiting for HS/LP DATA FIFO !full Timeout waiting for DBI FIFO empty Timeout waiting for read data. Same special packet %02x twice in a row. Video mode command 0x%08x send failed. Unsupported Mipi device to reg basevbt-generic-dsi-vid-mode-displaybpp match assertion failure (expected %d, current %d) /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_dsi_pll.cUnsupported MIPI element, skipping sequence execution Burst mode freq is less than computed Values crossing maximum limits, restricting to max values Generic Read not yet implemented or used DCS Read not yet implemented or used picking bpc to 12 for HDMI output picking bpc to 8 for HDMI output forcing pipe bpc to %i for HDMI too high HDMI clock, rejecting mode WARN_ON(!intel_crtc->config.has_hdmi_sink)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_hdmi.cEnabling HDMI audio on pipe %c Writing DIP with CTL reg disabled /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_drv.hHDMI port enabled, expecting disabled GMBUS [%s] timed out waiting for idle GMBUS [%s] timed out after NAK GMBUS [%s] NAK for addr: %04x %c(%d) GMBUS [%s] NAK on first message, retry 6[drm] GMBUS [%s] timed out, falling back to bit banging on pin %d WARN_ON(!intel_gmbus_is_port_valid(port))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_i2c.c%sabling bit-banging on %s. force bit now %d 6[drm] Skipping forced modeset for %s 6[drm] Skipping LVDS initialization for %s 6[drm] Forcing lvds to dual link mode on %s forcing display bpp (was %d) to LVDS (%d) timed out waiting for panel to power on timed out waiting for panel to power off using preferred mode from EDID: LVDS downclock is found in EDID. Normal clock %dKhz, downclock %dKhz detected %s-link lvds configuration lid notifier registration failed No LVDS modes found, disabling. Apple Mac Mini (Core 2 series)WARN_ON(source_min > source_max)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_panel.cWARN_ON(target_min > target_max)WARN_ON(panel->backlight.max == 0)WARN_ON(pipe != PIPE_A && pipe != PIPE_B)clamping VBT min backlight %d/255 to %d/255 pch backlight already enabled cpu backlight already enabled updating intel_backlight, brightness=%d/%d Skipping backlight disable on vga switch no backlight present per VBT, but present per quirk failed to setup backlight for connector %s Connector %s backlight initialized, %s, brightness %u/%u WARN_ON(panel->backlight.device)Failed to register backlight: %ld Connector %s backlight sysfs interface registered connector_is_digital? %d, monitor_is_digital? %d /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/intel_sdvo.ch_overscan: max %d, default %d, current %d v_overscan: max %d, default %d, current %d hpos: max %d, default %d, current %d vpos: max %d, default %d, current %d saturation: max %d, default %d, current %d contrast: max %d, default %d, current %d hue: max %d, default %d, current %d sharpness: max %d, default %d, current %d brightness: max %d, default %d, current %d flicker_filter: max %d, default %d, current %d flicker_filter_adaptive: max %d, default %d, current %d flicker_filter_2d: max %d, default %d, current %d tv_chroma_filter: max %d, default %d, current %d tv_luma_filter: max %d, default %d, current %d SDVO pixel multiplier mismatch, port: %i, encoder: %i First %s output reported failure to sync SDVO TV clock out of range: %i writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i 6[drm] Setting output timings on %s failed 6[drm] Setting input timings on %s failed unknown pixel mutlipler specified initialising analog device %d SDVO capabilities: vendor_id: %d device_id: %d device_rev_id: %d sdvo_version_major: %d sdvo_version_minor: %d sdvo_inputs_mask: %d smooth_scaling: %d sharp_scaling: %d up_scaling: %d down_scaling: %d stall_support: %d output_flags: %d %s: Unknown SDVO output type (0x%02x%02x) SDVO output failed to setup on %s %s device VID/DID: %02X:%02X.%02X, clock range %dMHz - %dMHz, input 1: %c, input 2: %c, output 1: %c, output 2: %c SDVO_CMD_GET_ATTACHED_DISPLAYSSDVO_CMD_GET_INTERRUPT_EVENT_SOURCESDVO_CMD_GET_INPUT_TIMINGS_PART1SDVO_CMD_GET_INPUT_TIMINGS_PART2SDVO_CMD_SET_INPUT_TIMINGS_PART1SDVO_CMD_SET_INPUT_TIMINGS_PART2SDVO_CMD_SET_OUTPUT_TIMINGS_PART1SDVO_CMD_SET_OUTPUT_TIMINGS_PART2SDVO_CMD_GET_OUTPUT_TIMINGS_PART1SDVO_CMD_GET_OUTPUT_TIMINGS_PART2SDVO_CMD_CREATE_PREFERRED_INPUT_TIMINGSDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGESDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGESDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTSSDVO_CMD_GET_SUPPORTED_TV_FORMATSSDVO_CMD_GET_SUPPORTED_POWER_STATESSDVO_CMD_SET_ENCODER_POWER_STATESDVO_CMD_SET_DISPLAY_POWER_STATESDVO_CMD_SET_CONTROL_BUS_SWITCHSDVO_CMD_GET_SDTV_RESOLUTION_SUPPORTSDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORTSDVO_CMD_GET_SUPPORTED_ENHANCEMENTSSDVO_CMD_GET_MAX_FLICKER_FILTERSDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVESDVO_CMD_GET_FLICKER_FILTER_ADAPTIVESDVO_CMD_SET_FLICKER_FILTER_ADAPTIVESDVO_CMD_GET_MAX_FLICKER_FILTER_2DSDVO_CMD_GET_FLICKER_FILTER_2DSDVO_CMD_SET_FLICKER_FILTER_2DSDVO_CMD_GET_MAX_TV_CHROMA_FILTERSDVO_CMD_GET_MAX_TV_LUMA_FILTERSDVO_CMD_GET_AUDIO_ENCRYPT_PREFERDetected Composite TV connection Detected S-Video TV connection Detected Component TV connection Integrated TV is not present. 6[drm] Your hardware requires kernel modesetting (KMS) 6[drm] See CONFIG_DRM_I915_KMS, nomodeset, and i915.modeset parameters &dev_priv->modeset_restore_locki915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s6[drm] This is an early pre-production Haswell machine. It may not be fully functional. failed to remove conflicting framebuffer drivers 6[drm] Replacing VGA console driver failed to remove conflicting VGA console Failed to create our workqueue. Failed to create our dp workqueue. 6[drm] Display disabled (module parameter) 6[drm] Display fused off, disabling 6[drm] failed to find VBIOS tables WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/drivers/gpu/drm/i915/i915_dma.c/`,/`,,,/`/`/`/`/`/`/`/`/`/`/`,,,/,`,,,/`,/`/`/` /`/`/`/`/`//``//``//`//``/``,,.-/`/`/`/`/`/`/`/`/`/`/`/`//``/`/`/`/`/`/`/`/`,,,,,,,,,,,/`,,,/`/`,,,,,,///``/``,,,,,,,,,/,/``/`/`/`,,,,,,,,././,,,,,,,,,,,,,,,,,,,,//``timeout disabling GT waking Found Ibex Peak PCH WARN_ON(!IS_GEN5(dev))Found CougarPoint PCH Found PantherPoint PCH Found LynxPoint PCH Found LynxPoint LP PCH Found SunrisePoint PCH WARN_ON(!IS_SKYLAKE(dev))Found SunrisePoint LP PCH No PCH found. Failed to reset chip: %i Failed hw init on reset %d offSuspend complete failed: %d dev: %p WARN_ON(!__warned)Suspending device Device suspended Resuming device Device resumed KMS and UMS disabled. i915Intel Graphics20141121Resetting error state %d %x bogus CZ count value%u l3 parity sysfs setup failed RPS sysfs setup failed errorgt_RPn_freq_mhzgt_RP1_freq_mhzgt_RP0_freq_mhzvlv_rpe_freq_mhzgt_min_freq_mhzgt_max_freq_mhzgt_cur_freq_mhzl3_parity_slice_1l3_parityrc6pp_residency_msrc6p_residency_msrc6_residency_msrc6_enableonoffEnabling RC6 states: RC6 %s BAFIFO size - (0x%08x) %s: %d FIFO watermark level: %ld flush pipe %c (pass %d) enabled fbc on plane %c Pixel clock is zero! Pixel size is zero! Latency value missing SR latency is 0, disabling disabled FBC FBC idle timed out no output, disabling disabled per chip default enableddisabledmemory self-refresh is %s self-refresh entries: %d DSPFW1 register is %x DSPFW3 register is %x WARN_ON(wm_lp != 1)WARN_ON(!r->enable)WARN_ON(!wm_changed)%s WM%d latency not provided ips_link_to_i915_driverWARN_ON(!dev_priv->vlv_pctx)bad pxval: %ld SKL Mailbox read error = %d 32unknown fsb frequency 0x%04x Gen9 PlanePrimarySpriteCursorOdd GPU freq value timed out waiting for Punit PCBR: 0x%08x DDR speed: %d MHz max GPU freq: %d MHz (%u) RPe GPU freq: %d MHz (%u) min GPU freq: %d MHz (%u) Odd GPU freq values yesnoGPLL not enabled GPLL enabled? %s GPU status: 0x%08x 6[drm] RC6 %s &dev_priv->rps.hw_lockWARN_ON(ctrl != state)WARN_ON(ctrl << 16 != state)Enabling power well Timeout enabling power well WARN_ON(!__warned)&power_domains->lockDevice still suspended. enabling %s WARN_ON(!power_well->count)disabling %s always-onpipe-adpio-common-bcdpio-common-ddisplaydpio-tx-b-01dpio-tx-b-23dpio-tx-c-01dpio-tx-c-23dpio-commonyesnoLLC: %s eLLC: %zuMB Current sequence (%s): %u gen: %d pch: %d is_mobile: %s is_i85x: %s is_i915g: %s is_i945gm: %s is_g33: %s need_gfx_hws: %s is_g4x: %s is_pineview: %s is_broadwater: %s is_crestline: %s is_ivybridge: %s is_valleyview: %s is_haswell: %s is_skylake: %s is_preliminary: %s has_fbc: %s has_pipe_cxsr: %s has_hotplug: %s cursor_needs_physical: %s has_overlay: %s overlay_needs_physical: %s supports_tv: %s has_llc: %s has_ddi: %s has_fpga_dbg: %s %c %s SizeEndStart%-15s%8s%8s%8s Pipe %c Cursor %-13s%8u%8u%8u Plane%-8d%8u%8u%8u DPLL%i: %s, id: %i tracked hardware state: dpll: 0x%08x dpll_md: 0x%08x fp0: 0x%08x fp1: 0x%08x wrpll: 0x%08x %lluenableddisabledself-refresh: %s OKFAILWorkarounds applied: %d not supported GPU idle: %s IRQs disabled: %s bugDDC = 0x%08x DDC2 = 0x%08x C0DRB3 = 0x%04x C1DRB3 = 0x%04x MAD_DIMM_C0 = 0x%08x MAD_DIMM_C1 = 0x%08x MAD_DIMM_C2 = 0x%08x TILECTL = 0x%08x GAMTARBMODE = 0x%08x ARB_MODE = 0x%08x DISP_ARB_CTL = 0x%08x L-shaped memory detected Currently: unknown Currently: enabled Currently: disabled %s requests: %d @ %d No requests PIPE_APIPE_BPIPE_CPIPE_A_PANEL_FITTERPIPE_B_PANEL_FITTERPIPE_C_PANEL_FITTERTRANSCODER_ATRANSCODER_BTRANSCODER_CTRANSCODER_EDPPORT_DDI_A_2_LANESPORT_DDI_A_4_LANESPORT_DDI_B_2_LANESPORT_DDI_B_4_LANESPORT_DDI_C_2_LANESPORT_DDI_C_4_LANESPORT_DDI_D_2_LANESPORT_DDI_D_4_LANESPORT_DSIPORT_CRTPORT_OTHERVGAAUDIOPLLSINITUse countPower well/domain%-25s %s %-25s %d %-23s %d nonexisting DP port %c %02x%02x%02x%02x%02x%02x Sink_Support: %s Source_OK: %s Enabled: %s Active: %s Re-enable work scheduled: %s HW Enabled & Active bit: %s Performance_Counter: %u Page directories: %d Page tables: %d %s PDP%d 0x%016llx GFX_MODE: 0x%08x PP_DIR_BASE: 0x%08x PP_DIR_BASE_READ: 0x%08x PP_DIR_DCLV: 0x%08x aliasing PPGTT: pd gtt offset: 0x%08x ECOCHK: 0x%08x proc: %s Status pointer: 0x%08X %d requests in queue Head request id: %u Head request tail: %u purgeable dirtyg XYPp (name: %d) (pinned x %d) (display) (fence: %d) (pp (g (stolen: %08lx) (%s mappable) (%s) (frontbuffer: 0x%03x)Reserved fences = %d Total fences = %d unusedActive: Inactive: FBC enabled FBC disabled: unsupported by this chipsetno outputsnot enough stolen memorymode not supportedmode too largeFBC unsupported on planescanout buffer not tiledmultiple pipes are enableddisabled per chip defaultunknown reasonunsupported on this chipset %d %d %d GMCH temp: %ld Chipset power: %ld GFX power: %ld Total power: %ld Requested P-state: %d Requested VID: %d Current VID: %d Current P-state: %d GT_PERF_STATUS: 0x%08x Render p-state ratio: %d Render p-state VID: %d Render p-state limit: %d RPSTAT1: 0x%08x RPMODECTL: 0x%08x RPINCLIMIT: 0x%08x RPDECLIMIT: 0x%08x RPNSWREQ: %dMHz CAGF: %dMHz RP CUR UP EI: %dus RP CUR UP: %dus RP PREV UP: %dus RP CUR DOWN EI: %dus RP CUR DOWN: %dus RP PREV DOWN: %dus DDR freq: %d MHz max GPU freq: %d MHz min GPU freq: %d MHz current GPU freq: %d MHz no P-state info available Display IER: %08x Display IIR: %08x Display IIR_RW: %08x Display IMR: %08x Port hotplug: %08x DPFLIPSTAT: %08x DPINVGTT: %08x Pipe %c stat: %08x GT Interrupt IMR %d: %08x GT Interrupt IIR %d: %08x GT Interrupt IER %d: %08x PCU interrupt mask: %08x PCU interrupt identity: %08x PCU interrupt enable: %08x Pipe %c power disabled Pipe %c IMR: %08x Pipe %c IIR: %08x Pipe %c IER: %08x Master IER: %08x Render IER: %08x Render IIR: %08x Render IMR: %08x PM IER: %08x PM IIR: %08x PM IMR: %08x Interrupt enable: %08x Interrupt identity: %08x Interrupt mask: %08x Pipe %c stat: %08x Stolen: %u objects, %zu bytes %zu [%lu] gtt total %llu 0x%llx 0x%08llx WM%d %u (%u.%u usec) Stopping rings 0x%08llx Resetting error state Dropping caches: 0x%08llx no ppgtt for context %d default context: context %d: power context render context HW context (default context %s) %s: Semaphores are disabled Last signal:0x%08llx (0x%02llx) 0x%08x Sync seqno: 0x%08x Last wait: CRTC info --------- Connector info -------------- primary plane disabled , mode: name: %s subpixel order: %s CEA rev: %d DPCD rev: %x audio support: %s fixed mode: modes: CONTEXT: %s %u Not bound in GGTT WARN_ON(page == NULL)fw_rendercount = %u fw_mediacount = %u forcewake count = %u Stall check enabled, %d prepares MMIO update completed? %d WARN_ON(!IS_G4X(dev))stopping CRCs for pipe %c pipeunknown object %s unknown pipe %s unknown source %s UpDownVideo Turbo Mode: %s HW control enabled: %s SW control enabled: %s RC6 Enabled: %s Render Power Well: %s Media Power Well: %s Forcewake Render Count = %u Forcewake Media Count = %u RC information accurate: %s RC1e Enabled: %s Deep RC6 Enabled: %s Deepest RC6 Enabled: %s Current RC state: Core Power Down on RC3 RC6 RC7 Unknown Core Power Down: %s RC6 residency since boot: %u RC6 voltage: %dmV RC6+ voltage: %dmV RC6++ voltage: %dmV HD boost: %s Boost freq: %d Gated voltage change: %s Starting frequency: P%d Max P-state: P%d Min P-state: P%d RS1 VID: %d RS2 VID: %d Render standby enabled: %s Current RS state: RC1 RC1E RS1 RS2 (RC6) RC3 (RC6+) unknown Turbo enabled: %s %8u %8x %8x %8x %8x %8x &pipe_crc->wqi915_forcewake_usernonebit9bit9/bit10bit9/bit11bit9/bit10/bit11unknownbit9/bit17bit9/bit10/bit17i915_wedgedi915_max_freqi915_min_freqi915_cache_sharingi915_ring_stopi915_ring_missed_irqi915_ring_test_irqi915_gem_drop_cachesi915_error_statei915_next_seqnoi915_display_crc_ctli915_pri_wm_latencyi915_spr_wm_latencyi915_cur_wm_latencyi915_fbc_false_colori915_capabilitiesi915_gem_objectsi915_gem_gtti915_gem_pinnedi915_gem_activei915_gem_inactivei915_gem_stoleni915_gem_pageflipi915_gem_requesti915_gem_seqnoi915_gem_fence_regsi915_gem_interrupti915_gem_hwsi915_gem_hws_blti915_gem_hws_bsdi915_gem_hws_veboxi915_frequency_infoi915_drpc_infoi915_emon_statusi915_ring_freq_tablei915_fbc_statusi915_ips_statusi915_sr_statusi915_opregioni915_gem_framebufferi915_context_statusi915_dump_lrci915_execlistsi915_gen6_forcewake_counti915_swizzle_infoi915_ppgtt_infoi915_llci915_edp_psr_statusi915_sink_crc_eDP1i915_energy_uJi915_pc8_statusi915_power_domain_infoi915_display_infoi915_semaphore_statusi915_shared_dplls_infoi915_dp_mst_infoi915_wa_registersi915_ddb_infoplane1plane2pfTVDP-BDP-CDP-Dautoi915_pipe_A_crci915_pipe_B_crci915_pipe_C_crcCMD: cmd_parser_init failed! CMD: failed to prep read Failed to vmap pages CMD: Failed to vmap batch WARN_ON(ret)Couldn't pin %d PPGTT setup failed (%ld) fakeLRHWL3 remapping failed ring init context: %d init render state: %d HW context %d created HW context %d destroyed WARN_ON(ring->id != RCS)only %d relocs resolved i915WARN_ON(i915_vma_unbind(vma))Failed to lookup VMA execbuf with %d buffers Could not create LRC %u: %d execbuf with %u cliprects no rel constants on pre-gen4 sol reset is gen7/rcs only Bad box %d,%d..%d,%d execbuf2 with %d buffers dirty rvsd2 field VM %p (pd_offset %x-%x): PDE: %x 0x%lx [%03d,%04d]: = %08x SCRATCH WARN_ON(1)failed to set up gmch Scratch setup failed Unknown GMADR size (%lx) Adding PPGTT at offset %x GGTTPPGTTCouldn't idle GPU Reservation failed: %i GMADR size = %ldM GTT stolen size = %zdM ppgtt mode: %i WARN_ON(i915_is_ggtt(vm))IRQs disabledWARN_ON(!ring->irq_get(ring))WARN_ON(request == NULL)WARN_ON(ret != -EIO)WARN_ON(vma->node.allocated)PPGTT enable failed %d Context enable failed %d allow wake ack timed out globalppgttWARN_ON(fence->pin_count)mappabletotalWARN_ON(ret == -ERESTARTSYS)WARN_ON(i915_vma_unbind(vma))WARN_ON(obj->pages_pin_count)WARN_ON(!ctx)i915_gem_object&dev_priv->pending_flip_queue&dev_priv->fb_tracking.lockoffset=0x%x, size=%d Graphics Stolen Memoryunknown tiling mode WARN_ON(ret && ret != -EIO)&dev_priv->mm_lockoverflow%08x : %08x P p X Y dirty purgeable userptr uncached snooped L3+LLC WT LLC %s [%d]: %08x %8u %02x %02x %x %x (name: %d) (fence: %d) yesnounknownno error state collected %s Time: %ld s %ld us Kernel: 3.19.0-80-generic Reset count: %u Suspend count: %u PCI ID: 0x%04x EIR: 0x%08x IER: 0x%08x GTIER gt %d: 0x%08x GTIER: 0x%08x PGTBL_ER: 0x%08x FORCEWAKE: 0x%08x DERRMR: 0x%08x CCID: 0x%08x Missed interrupts: 0x%08lx fence[%d] = %08llx INSTDONE_%d: 0x%08x ERROR: 0x%08x DONE_REG: 0x%08x ERR_INT: 0x%08x %s command stream: HEAD: 0x%08x TAIL: 0x%08x CTL: 0x%08x HWS: 0x%08x ACTHD: 0x%08x %08x IPEIR: 0x%08x IPEHR: 0x%08x INSTDONE: 0x%08x BBADDR: 0x%08x %08x BB_STATE: 0x%08x INSTPS: 0x%08x INSTPM: 0x%08x FADDR: 0x%08x %08x RC PSMI: 0x%08x FAULT_REG: 0x%08x GFX_MODE: 0x%08x PDP%d: 0x%016llx PP_DIR_BASE: 0x%08x seqno: 0x%08x waiting: %s ring->head: 0x%08x ring->tail: 0x%08x hangcheck: %s [%d] vm[%d] ActivePinned (submitted by %s [%d]) --- gtt_offset = 0x%08x %s --- %d requests %s --- ringbuffer = 0x%08x %s --- HW Status = 0x%08x [%04x] %08x %08x %08x %08x %s --- HW Context = 0x%08x Semaphore page = 0x%08x Unsupported platform resetcontinueGPU HANG: ecode %d:%d:0x%08x, in %s [%d], reason: %s, action: %s6[drm] %s idlewaitactiveactive (loop)kickhungrenderbsdbltveboxbsd2spurious interrupt CRC buffer overflowing WARN_ON(!__warned)L3_PARITY_ERROR=1ROW=%dBANK=%dSUBBANK=%dSLICE=%dERROR=1RESET=1ERROR=0resetting chip Invalid crtc %d crtc %d is disabled longshortdigital hpd port %c - %s Audio CP request interrupt Audio CP change interrupt pipe %c FDI IIR: 0x%08x PCH poison interrupt GEN9+: unexpected RPS IRQ Poison interrupt PCH HDCP audio interrupt Unexpected DE Misc interrupt Unexpected DE Port interrupt WARN_ON(dev_priv->rps.pm_iir)3i915: IPEIR: 0x%08x 3i915: IPEHR: 0x%08x 3i915: INSTPS: 0x%08x 3i915: ACTHD: 0x%08x 3i915: page table error 3i915: PGTBL_ER: 0x%08x 3i915: pipe %c stat: 0x%08x 3i915: instruction error 3i915: INSTPM: 0x%08x EIR stuck: 0x%08x, masking stuckno progressKicking stuck wait on %sKicking stuck semaphore on %s6[drm] %s on %s Ring hungobjstruct drm_i915_gem_object *devu32freqobj=%p, size=%u , mappableobj=%p, offset=%u, len=%u , writableGTTCPUobj=%p, %s index=%u %s obj=%p dev=%d, size=%d, align=%d %s dev=%d dev=%d, vm=%p dev=%u, ring=%u, seqno=%u yes (NB)nodev=%u, ring=%u plane=%d, obj=%p writereadnew_freq=%u dev=%u, vm=%p dev=%u, ctx=%p, ctx_vm=%p pipeenum pipeframescanlineminmaxsizevmstruct i915_address_space *offsetflagsunsignedread_domainswrite_domainlenindexgttboolalignsync_fromsync_toseqnoringinvalidateflushblockingplaneintvalu64regu16ctxstruct intel_context *toi915Never submitted head request Execlists enabled for %s sol reset is gen7 only WARN_ON(w->count == 0)Could not set to CPU domain Could not get object pages Failed to populate LRC: %d ring init context: %d Init render state failed: %d &ring->irq_queuerender ringbsd ringblitter ringvideo enhancement ringbds2 ringWARN_ON(ring->id != RCS)&ring->irq_queue%s hws offset: 0x%08x render ringFailed to allocate batch bo Failed to ping batch bo bsd ringbsd2 ringblitter ringvideo enhancement ringWARN_ON(w->count == 0)Device suspended GT wake FIFO error 0x%x readingwriting tobeforeafter6[drm] Found %zuMB of eLLC WARN_ON(1)Disable audio codec WARN_ON(!port)WARN_ON(!__warned)ELD size %d VBT signature missing VBT header incomplete $VBTVBT invalid signature BDB header incomplete BDB incomplete Using VBT from %s: %20s lowhighSDVOBSDVOCSet default to SSC at %d kHz OpRegionPCI ROMcrt_ddc_bus_pin: %d VBT initial LVDS value %x Incorrect SDVO port. Skip it Found MIPI as LFP DRRS State Enabled:%d No MIPI config BDB foundFound MIPI sequence block Found mipi sequence - %d undefined sequence Unknown element Port %c is analog Port %c is TMDS compatible Port %c is internal DP ThinkCentre A57onoffdisabling fdi C rx enabling fdi C rx enabling CxSR downclocking disabling CxSR downclocking WARN_ON(1)FDI_RX_IIR 0x%x FDI train 1 done, level %i. FDI train 2 done, level %i. FDI train done. FDI train 1 done. FDI train 2 done. FDI train 1 fail! FDI train 2 fail! tiledlinearunsupported pixel format: %s framebuffer init failed %d cdclk change in progress cursor off failed to attach phys object buffer is too small cursor cannot be tiled WARN_ON(!__warned)Failed to write to D_COMP enableddisabledcpu_transcoder: %c pipe bpp: %i, dithering: %i audio: %i, infoframes: %i requested mode: adjusted mode: port clock: %d pipe src size: %dx%d ips: %i double wide: %i [CRTC:%d] pipe state doesn't match! [hw state][sw state]LP PCH doesn't have FDI intel fb init failed plane fb obj %p %s pll hw state mismatch pipe_off wait timed out failed to alloc fb WARN_ON(!HAS_PCH_SPLIT(dev))WARN_ON(pll == NULL)WARN_ON(pll->active == 0)WARN_ON(!pll->on)disabling %s WARN_ON(pll->on)enabling %s WARN_ON(HAS_DDI(dev))PLL %d failed to lock DPLL %d failed to lock FDI train done No FB bound pin & fence failed WARN_ON(obj == NULL)Removing stuck page flip bad %s crtc mask WARN_ON(pll->active)CRTC:%d allocated %s using %s for pipe %c Unexpected PCH type %d WARN_ON(!crtc->enabled)WARN_ON(!encoder->new_crtc)WARN_ON(!HAS_DDI(dev))unsupported depth Encoder config failure CRTC fixup failed [modeset]setting up %s Using SSC on panel Using SSC on eDP Disabling SSC entirely probing SDVOB probing HDMI on SDVOB probing SDVOC probing HDMI on SDVOC Enabling package C8+ CRTC for pipe %c enabled Power well on SPLL enabled WRPLL1 enabled WRPLL2 enabled Panel power on CPU PWM1 enabled CPU PWM2 enabled PCH PWM1 enabled Utility pin enabled PCH GTC enabled IRQs enabled Switching to FCLK failed LCPLL still locked Disabling package C8+ LCPLL not locked yet downclocking LVDS failed to downclock LVDS! WARN_ON(!in_interrupt())[CONNECTOR:%d:%s] wrong connector dpms state encoder not enabled WARN_ON(!encoder->base.crtc)crtc not enabled crtc not active [ENCODER:%d:%s] active encoder with no crtc endis[CRTC:%d] [NOFB] crtc has no fb, will flip inactive crtc, full mode set WARN_ON(!intel_crtc->active)WARN_ON(!encoder->crtc)no such CRTC id Invalid[CRTC:%d] found active mode: WARN_ON(crtc->active)[setup_hw_state]s&dev_priv->pps_mutex%d display pipe%s available. PCH DPLL APCH DPLL Bfailed to read control word failed to write control word Num Pipes: %d PWR_WELL_CTL2: %08x Pipe [%d]: Power: %s SRC: %08x STAT: %08x Plane [%d]: CNTR: %08x STRIDE: %08x SIZE: %08x POS: %08x ADDR: %08x SURF: %08x TILEOFF: %08x Cursor [%d]: BASE: %08x CPU transcoder: %c CONF: %08x HTOTAL: %08x HBLANK: %08x HSYNC: %08x VTOTAL: %08x VBLANK: %08x VSYNC: %08x UnusedAnalogDVOSDVOLVDSTVHDMIDisplayPorteDPDSIUnknownNCR Corporationpipe %c underrun CPU pipe %c FIFO underrun upclocking LVDS failed to upclock LVDS! audioBroadcast RGBAutomaticFullLimited 16:235force-dvioffautoonoverlay underrun, DOVSTA: %x userspace bug: no overlay WARN_ON(dev_priv->overlay) Register file at 0x%08lx: OBUF_0Y: 0x%08x OBUF_1Y: 0x%08x OBUF_0U: 0x%08x OBUF_0V: 0x%08x OBUF_1U: 0x%08x OBUF_1V: 0x%08x OSTRIDE: 0x%08x YRGB_VPH: 0x%08x UV_VPH: 0x%08x HORZ_PH: 0x%08x INIT_PHS: 0x%08x DWINPOS: 0x%08x DWINSZ: 0x%08x SWIDTH: 0x%08x SWIDTHSW: 0x%08x SHEIGHT: 0x%08x YRGBSCALE: 0x%08x UVSCALE: 0x%08x OCLRC0: 0x%08x OCLRC1: 0x%08x DCLRKV: 0x%08x DCLRKM: 0x%08x SCLRKVH: 0x%08x SCLRKVL: 0x%08x SCLRKEN: 0x%08x OCONFIG: 0x%08x OCMD: 0x%08x OSTART_0Y: 0x%08x OSTART_1Y: 0x%08x OSTART_0U: 0x%08x OSTART_0V: 0x%08x OSTART_1U: 0x%08x OSTART_1V: 0x%08x OTILEOFF_0Y: 0x%08x OTILEOFF_1Y: 0x%08x OTILEOFF_0U: 0x%08x OTILEOFF_0V: 0x%08x OTILEOFF_1U: 0x%08x OTILEOFF_1V: 0x%08x FASTHSCALE: 0x%08x UVSCALEV: 0x%08x WARN_ON(dev_priv->psr.active)PSR already in use HSW ties PSR to DDI A (eDP) PSR disable by flag &dev_priv->psr.lockreadwriteWARN_ON(!plane->crtc)Wrong plane <-> crtc mapping Unsupported tiling mode bad typefailed to evaluate _DSM MUX info connectors: %lld Connector id: 0x%016llx port id: %s display mux info: %s aux/dc mux info: %s hpd mux info: %s unknownNo MUX, iGPU onlyNo MUX, dGPU onlyMUXed between iGPU and dGPUReservedAnalog VGALVDSHDMI/DVI_BHDMI/DVI_CHDMI/DVI_DDisplayPort_ADisplayPort_BDisplayPort_CDisplayPort_DWiDiSWSCI request timed out SWSCI request error %u Illum is not supported bclp = 0x%08x Pfit is not supported PWM freq is not supported SROT is not supported ISCT is not supported video_ADRACPI OpRegion not supported! IntelGraphicsMemopregion signature mismatch SWSCI supported ASLE supported i915iWARN_ON(!encoder->crtc)Enabled: %i, detected: %i failed to pin obj: %d WARN_ON(!intel_fb->obj)re-using BIOS fb pipe %c not active, skipping failed to restore crtc mode CH7017_LVDS_CONTROL_2: %02x CH7017_OUTPUTS_ENABLE: %02x CH7017_LVDS_POWER_DOWN: %02x Registers after mode setting ch7017ch7018ch7019%s detected on %s, addr %d %02X: %02X CH7XXXCH7010BCH7011CH7009ACH7009BCH7301VR00: 0x%04x VR01: 0x%04x VR30: 0x%04x VR40: 0x%04x VR80: 0x%04x VR81: 0x%04x VR82: 0x%04x VR83: 0x%04x VR84: 0x%04x VR85: 0x%04x VR86: 0x%04x VR87: 0x%04x VR88: 0x%04x VR8E: 0x%04x VR8F: 0x%04x SIL164_FREQ_LO: 0x%02x SIL164_FREQ_HI: 0x%02x SIL164_REG8: 0x%02x SIL164_REG9: 0x%02x SIL164_REGC: 0x%02x TFP410_REV: 0x%02X TFP410_CTL1: 0x%02X TFP410_CTL2: 0x%02X TFP410_CTL3: 0x%02X TFP410_USERCFG: 0x%02X TFP410_DE_DLY: 0x%02X TFP410_DE_CTL: 0x%02X TFP410_DE_TOP: 0x%02X TFP410_DE_CNT: 0x%02X%02X TFP410_DE_LIN: 0x%02X%02X TFP410_H_RES: 0x%02X%02X TFP410_V_RES: 0x%02X%02X crt adpa set to 0x%x Disabling SPLL SPLL already enabled LPT only supports 24bpp [CONNECTOR:%d:%s] force=%d CRT detected via hotplug CRT not detected via hotplug starting load-detect on CRT ACER ZGBDELL XPS 8700DPLL %d not locked bad wrpll refclk bad spll freq bad port clock sel Unsupported link rate Invalid DDI encoder type %d WARN_ON(dpll != SKL_DPLL0)FDI link training failed! Incorrect PDiv Incorrect KDiv LCPLL1 not enabled Unknown cd freq selection DPLL 1DPLL 2DPLL 3WRPLL 1WRPLL 2CDCLK running at %dKHz LCPLL1 is disabled CDCLK source is not LCPLL LCPLL is disabled WARN_ON(HAS_DDI(dev)) DPCD: %*ph Detected EDP PSR Panel. Displayport TPS3 supported [CONNECTOR:%d:%s] no scaling not supported dp pll off, should be on eDP PLL enable for clock %d dp pll on, should be off Turning eDP port %c VDD off WARN_ON(!is_edp(intel_dp))WARN_ON(pipes == 0)Sink OUI: %02hx%02hx%02hx Branch OUI: %02hx%02hx%02hx Sink is MST capable Sink is not MST capable Wait complete Wait for panel power cycle Turning eDP port %c VDD on Status 0x%08x Control 0x%08x eDP port %c VDD not forced onWARN_ON(txsize > 20)WARN_ON(rxsize > 20)Wait for panel power on Using signal levels %08x enabledisableWARN_ON(!IS_VALLEYVIEW(dev))failed to get link status clock recovery OK failed to train DP, aborting got esi %02x %02x %02x got esi2 %02x %02x %02x WARN_ON(dp_reg & DP_PORT_EN)Enabling DP audio on pipe %c longshortgot hpd irq on port %c - %s DRRS supported for eDP only. eDPDPDPDDC-ADPDDC-BDPDDC-CDPDDC-Dregistering %s bus for %s VBT doesn't support DRRS DRRS not supported &intel_dp->drrs_state.mutex%d can't find connector failed to allocate vcpi failed to update payload %d RXSOT_ERROR RXSOT_SYNC_ERROR RXEOT_SYNC_ERROR RXEXCAPE_MODE_ENTRY_ERROR RX_LP_TX_SYNC_ERROR RXHS_RECEIVE_TIMEOUT_ERROR RXFALSE_CONTROL_ERROR RXECC_SINGLE_BIT_ERROR RXECC_MULTIBIT_ERROR RXCHECKSUM_ERROR RXDSI_VC_ID_INVALID TXFALSE_CONTROL_ERROR TXECC_SINGLE_BIT_ERROR TXECC_MULTIBIT_ERROR TXCHECKSUM_ERROR TXDSI_VC_ID_INVALID HIGH_CONTENTION LOW_CONTENTION DPI_FIFO_UNDERRUN HS_TX_TIMEOUT LP_RX_TIMEOUT TURN_AROUND_ACK_TIMEOUT ACK_WITH_NO_ERROR RX_INVALID_TX_LENGTH RX_PROT_VIOLATION HS_GENERIC_WR_FIFO_FULL LP_GENERIC_WR_FIFO_FULL GEN_READ_DATA_AVAIL SPL_PKT_SENT_INTERRUPT TEARING_EFFECTDPI FIFOs are not empty pipe %c DSI LP not going Low MODE_NO_DBLESCAN no fixed mode drm_mode_duplicate failed no device found DSI CLK Out of Range dsi_calc_mnp failed dsi pll div %08x, ctrl %08x DSI PLL locked DSI PLL lock failed wrong P1 divisor wrong m_seed programmed Starting MIPI sequence - %s enableddisabledcommandvideo Burst mode target is not set Eot %s Clockstop %s Mode %s Pixel Format %d TLPX %d LP RX Timeout 0x%x Turnaround Timeout 0x%x Init Count 0x%x HS to LP Count 0x%x LP Byte Clock %d DBI BW Timer 0x%x LP to HS Clock Count 0x%x HS to LP Clock Count 0x%x BTA %s unknown gpio %u UNDEFINEDMIPI_SEQ_ASSERT_RESETMIPI_SEQ_INIT_OTPMIPI_SEQ_DISPLAY_ONMIPI_SEQ_DISPLAY_OFFMIPI_SEQ_DEASSERT_RESET[CONNECTOR:%d:%s] sil164ch7xxxivchtfp410ch7017ns2501couldn't fill AVI infoframe Integrated gfxIntelcouldn't fill SPD infoframe [CONNECTOR:%d:%s] unknown info frame type %d &dev_priv->gmbus_mutex&dev_priv->gmbus_wait_queuei915 gmbus %sendissscvgapaneldpcdpbdpdCan't support LVDS on pipe A [CONNECTOR:%d:%s] no scaling not supported dualsingleLVDS is not present in VBT disable LVDS for eDP support using mode from VBT: using current (BIOS) mode: Apple MacBook Pro 15" (2010)Apple MacBook Pro 15" (2011)Apple MacBook Pro 15" (2012)Apple Mac Mini (Core series)MSI IM-945GSE-ADell Studio HybridDell OptiPlex FX170AOpen Mini PCAOpen Mini PC MP915AOpen i915GMm-HFSAOpen i45GMx-IAopen i945GTt-VFAClientron U800Clientron E830Asus EeeBox PC EB1007Asus AT5NM10T-IHewlett-Packard HP t5740Hewlett-Packard t5745Hewlett-Packard st5747MSI Wind Box DC500Gigabyte GA-D525TUDSupermicro X7SPA-HFujitsu Esprimo Q900Intel D410PTIntel D425KTIntel D510MOIntel D525MWToshiba Tecra A11set backlight PWM = %d backlight already enabled get backlight PWM = %d bad panel fit mode: %d pipe %c enableddisabledno backlight present per VBT intel_backlighti2c transfer returned %d SDVOBSDVOC(%s)(??? %d) %02X%s: R: %s %s: R: ... failed %02X %s: W: %02X %s (%02X)I2c transfer returned %d I2c transfer returned %d/%d left_marginright_margintop_marginbottom_marginhposvpossaturationcontrasthuesharpnessbrightnessflicker_filterflicker_filter_adaptiveflicker_filter_2dtv_chroma_filtertv_luma_filterdot_crawldot crawl: current %d No enhancement is supported failed to retrieve SDVO DTD forcing bpc to 8 for SDVO couldn't fill AVI infoframe [CONNECTOR:%d:%s] SDVO response %d %d [%x] initialising LVDS device %d initialising DVI device %d initialising TV type %d modeNo SDVO device found on %s Power onSuccessNot supportedInvalid argPendingTarget not specifiedScaling not supportedSDVO_CMD_RESETSDVO_CMD_GET_DEVICE_CAPSSDVO_CMD_GET_FIRMWARE_REVSDVO_CMD_GET_TRAINED_INPUTSSDVO_CMD_GET_ACTIVE_OUTPUTSSDVO_CMD_SET_ACTIVE_OUTPUTSSDVO_CMD_GET_IN_OUT_MAPSDVO_CMD_SET_IN_OUT_MAPSDVO_CMD_GET_HOT_PLUG_SUPPORTSDVO_CMD_SET_ACTIVE_HOT_PLUGSDVO_CMD_GET_ACTIVE_HOT_PLUGSDVO_CMD_SET_TARGET_INPUTSDVO_CMD_SET_TARGET_OUTPUTSDVO_CMD_GET_CLOCK_RATE_MULTSDVO_CMD_SET_CLOCK_RATE_MULTSDVO_CMD_GET_TV_FORMATSDVO_CMD_SET_TV_FORMATSDVO_CMD_GET_POWER_STATESDVO_CMD_GET_MAX_HPOSSDVO_CMD_GET_HPOSSDVO_CMD_SET_HPOSSDVO_CMD_GET_MAX_VPOSSDVO_CMD_GET_VPOSSDVO_CMD_SET_VPOSSDVO_CMD_GET_MAX_SATURATIONSDVO_CMD_GET_SATURATIONSDVO_CMD_SET_SATURATIONSDVO_CMD_GET_MAX_HUESDVO_CMD_GET_HUESDVO_CMD_SET_HUESDVO_CMD_GET_MAX_CONTRASTSDVO_CMD_GET_CONTRASTSDVO_CMD_SET_CONTRASTSDVO_CMD_GET_MAX_BRIGHTNESSSDVO_CMD_GET_BRIGHTNESSSDVO_CMD_SET_BRIGHTNESSSDVO_CMD_GET_MAX_OVERSCAN_HSDVO_CMD_GET_OVERSCAN_HSDVO_CMD_SET_OVERSCAN_HSDVO_CMD_GET_MAX_OVERSCAN_VSDVO_CMD_GET_OVERSCAN_VSDVO_CMD_SET_OVERSCAN_VSDVO_CMD_GET_FLICKER_FILTERSDVO_CMD_SET_FLICKER_FILTERSDVO_CMD_GET_MAX_SHARPNESSSDVO_CMD_GET_SHARPNESSSDVO_CMD_SET_SHARPNESSSDVO_CMD_GET_DOT_CRAWLSDVO_CMD_SET_DOT_CRAWLSDVO_CMD_GET_TV_CHROMA_FILTERSDVO_CMD_SET_TV_CHROMA_FILTERSDVO_CMD_GET_TV_LUMA_FILTERSDVO_CMD_SET_TV_LUMA_FILTERSDVO_CMD_GET_SUPP_ENCODESDVO_CMD_GET_ENCODESDVO_CMD_SET_ENCODESDVO_CMD_SET_PIXEL_REPLISDVO_CMD_GET_PIXEL_REPLISDVO_CMD_GET_COLORIMETRY_CAPSDVO_CMD_SET_COLORIMETRYSDVO_CMD_GET_COLORIMETRYSDVO_CMD_SET_AUDIO_STATSDVO_CMD_GET_AUDIO_STATSDVO_CMD_GET_HBUF_INDEXSDVO_CMD_SET_HBUF_INDEXSDVO_CMD_GET_HBUF_INFOSDVO_CMD_GET_HBUF_AV_SPLITSDVO_CMD_SET_HBUF_AV_SPLITSDVO_CMD_GET_HBUF_TXRATESDVO_CMD_SET_HBUF_TXRATESDVO_CMD_SET_HBUF_DATASDVO_CMD_GET_HBUF_DATANTSC_MNTSC_JNTSC_443PAL_BPAL_DPAL_GPAL_HPAL_IPAL_MPAL_NPAL_NCPAL_60SECAM_BSECAM_DSECAM_GSECAM_KSECAM_K1SECAM_LSECAM_60forcing bpc to 8 for TV [CONNECTOR:%d:%s] force=%d TV detected: %x, %x Unrecognised TV connection NTSC-M640x480800x6001024x7681280x1024848x4801280x7201920x1080NTSC-443NTSC-JPAL-MPAL-NPAL480p576p720p@60Hz720p@50Hz1080i@50Hz1080i@60Hzunknown parameter %d 6i915: switched on 3i915: switched off Unknown parameter %d copy_to_user failed has_fpga_dbg,has_ddi,has_llc,supports_tv,overlay_needs_physical,has_overlay,cursor_needs_physical,has_hotplug,has_pipe_cxsr,has_fbc,is_preliminary,is_skylake,is_haswell,is_valleyview,is_ivybridge,is_crestline,is_broadwater,is_pineview,is_g4x,need_gfx_hws,is_g33,is_i945gm,is_i915g,is_i85x,is_mobile,&dev_priv->backlight_lock&dev_priv->dpio_lockbridge device not found failed to map registers inteldrmfbi915i915-dpi915 MCHBARfailed bus alloc: %d failed to init modeset failed to idle hardware: %d I915_INITI915_FLUSHI915_FLIPI915_BATCHBUFFERI915_IRQ_EMITI915_IRQ_WAITI915_GETPARAMI915_SETPARAMI915_ALLOCI915_FREEI915_INIT_HEAPI915_CMDBUFFERI915_DESTROY_HEAPI915_SET_VBLANK_PIPEI915_GET_VBLANK_PIPEI915_VBLANK_SWAPI915_HWS_ADDRI915_GEM_INITI915_GEM_EXECBUFFERI915_GEM_PINI915_GEM_UNPINI915_GEM_BUSYI915_GEM_THROTTLEI915_GEM_ENTERVTI915_GEM_LEAVEVTI915_GEM_CREATEI915_GEM_PREADI915_GEM_PWRITEI915_GEM_MMAPI915_GEM_SET_DOMAINI915_GEM_SW_FINISHI915_GEM_SET_TILINGI915_GEM_GET_TILINGI915_GEM_GET_APERTUREI915_GEM_MMAP_GTTI915_GET_PIPE_FROM_CRTC_IDI915_GEM_MADVISEI915_OVERLAY_PUT_IMAGEI915_OVERLAY_ATTRSI915_GEM_EXECBUFFER2I915_GET_SPRITE_COLORKEYI915_SET_SPRITE_COLORKEYI915_GEM_WAITI915_GEM_CONTEXT_CREATEI915_GEM_CONTEXT_DESTROYI915_GEM_SET_CACHINGI915_GEM_GET_CACHINGI915_REG_READI915_GET_RESET_STATSI915_GEM_USERPTRlicense=GPL and additional rightsdescription=Intel Graphicsauthor=Intel Corporationauthor=Tungsten Graphics, Inc.parm=mmio_debug:Enable the MMIO debug code (default: false). This may negatively affect performance.parmtype=mmio_debug:boolparm=use_mmio_flip:use MMIO flips (-1=never, 0=driver discretion [default], 1=always)parmtype=use_mmio_flip:intparm=enable_cmd_parser:Enable command parsing (1=enabled [default], 0=disabled)parmtype=enable_cmd_parser:intparm=disable_vtd_wa:Disable all VT-d workarounds (default: false)parmtype=disable_vtd_wa:boolparm=disable_display:Disable display (default: false)parmtype=disable_display:boolparm=invert_brightness:Invert backlight brightness (-1 force normal, 0 machine defaults, 1 force inversion), please report PCI device ID, subsystem vendor and subsystem device ID to dri-devel@lists.freedesktop.org, if your machine needs it. It will then be included in an upcoming module version.parmtype=invert_brightness:intparm=prefault_disable:Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.parmtype=prefault_disable:boolparm=fastboot:Try to skip unnecessary mode sets at boot time (default: false)parmtype=fastboot:boolparm=enable_ips:Enable IPS (default: true)parmtype=enable_ips:intparm=disable_power_well:Disable the power well when possible (default: true)parmtype=disable_power_well:intparm=preliminary_hw_support:Enable preliminary hardware support.parmtype=preliminary_hw_support:intparm=enable_psr:Enable PSR (default: false)parmtype=enable_psr:intparm=enable_execlists:Override execlists usage. (-1=auto, 0=disabled [default], 1=enabled)parmtype=enable_execlists:intparm=enable_ppgtt:Override PPGTT usage. (-1=auto [default], 0=disabled, 1=aliasing, 2=full)parmtype=enable_ppgtt:intparm=enable_hangcheck:Periodically check GPU activity for detecting hangs. WARNING: Disabling this can cause system wide hangs. (default: true)parmtype=enable_hangcheck:boolparm=reset:Attempt GPU resets (default: true)parmtype=reset:boolparm=vbt_sdvo_panel_type:Override/Ignore selection of SDVO panel mode in the VBT (-2=ignore, -1=auto [default], index in VBT BIOS table)parmtype=vbt_sdvo_panel_type:intparm=lvds_use_ssc:Use Spread Spectrum Clock with panels [LVDS/eDP] (default: auto from VBT)parmtype=lvds_use_ssc:intparm=lvds_channel_mode:Specify LVDS channel mode (0=probe BIOS [default], 1=single-channel, 2=dual-channel)parmtype=lvds_channel_mode:intparm=lvds_downclock:Use panel (LVDS/eDP) downclocking for power savings (default: false)parmtype=lvds_downclock:intparm=enable_fbc:Enable frame buffer compression for power savings (default: -1 (use per-chip default))parmtype=enable_fbc:intparm=enable_rc6:Enable power-saving render C-state 6. Different stages can be selected via bitmask values (0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. default: -1 (use per-chip default)parmtype=enable_rc6:intparm=semaphores:Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))parmtype=semaphores:intparm=powersave:Enable powersavings, fbc, downclocking, etc. (default: true)parmtype=powersave:intparm=panel_ignore_lid:Override lid status (0=autodetect, 1=autodetect disabled [default], -1=force lid closed, -2=force lid open)parmtype=panel_ignore_lid:intparm=modeset:Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, 1=on, -1=force vga console preference [default])parmtype=modeset:intsrcversion=CD5BE23EB1D4D6E78E15E21alias=pci:v00008086d00000155sv*sd*bc03sc*i*alias=pci:v00008086d00000157sv*sd*bc03sc*i*alias=pci:v00008086d00000F33sv*sd*bc03sc*i*alias=pci:v00008086d00000F32sv*sd*bc03sc*i*alias=pci:v00008086d00000F31sv*sd*bc03sc*i*alias=pci:v00008086d00000F30sv*sd*bc03sc*i*alias=pci:v00008086d00000D26sv*sd*bc03sc*i*alias=pci:v00008086d00000D16sv*sd*bc03sc*i*alias=pci:v00008086d00000D06sv*sd*bc03sc*i*alias=pci:v00008086d00000A2Esv*sd*bc03sc*i*alias=pci:v00008086d00000A1Esv*sd*bc03sc*i*alias=pci:v00008086d00000A0Esv*sd*bc03sc*i*alias=pci:v00008086d00000A26sv*sd*bc03sc*i*alias=pci:v00008086d00000A16sv*sd*bc03sc*i*alias=pci:v00008086d00000A06sv*sd*bc03sc*i*alias=pci:v00008086d00000C26sv*sd*bc03sc*i*alias=pci:v00008086d00000C16sv*sd*bc03sc*i*alias=pci:v00008086d00000C06sv*sd*bc03sc*i*alias=pci:v00008086d00000426sv*sd*bc03sc*i*alias=pci:v00008086d00000416sv*sd*bc03sc*i*alias=pci:v00008086d00000406sv*sd*bc03sc*i*alias=pci:v00008086d00000D2Esv*sd*bc03sc*i*alias=pci:v00008086d00000D1Esv*sd*bc03sc*i*alias=pci:v00008086d00000D0Esv*sd*bc03sc*i*alias=pci:v00008086d00000D2Bsv*sd*bc03sc*i*alias=pci:v00008086d00000D1Bsv*sd*bc03sc*i*alias=pci:v00008086d00000D0Bsv*sd*bc03sc*i*alias=pci:v00008086d00000D2Asv*sd*bc03sc*i*alias=pci:v00008086d00000D1Asv*sd*bc03sc*i*alias=pci:v00008086d00000D0Asv*sd*bc03sc*i*alias=pci:v00008086d00000D22sv*sd*bc03sc*i*alias=pci:v00008086d00000D12sv*sd*bc03sc*i*alias=pci:v00008086d00000D02sv*sd*bc03sc*i*alias=pci:v00008086d00000A2Bsv*sd*bc03sc*i*alias=pci:v00008086d00000A1Bsv*sd*bc03sc*i*alias=pci:v00008086d00000A0Bsv*sd*bc03sc*i*alias=pci:v00008086d00000A2Asv*sd*bc03sc*i*alias=pci:v00008086d00000A1Asv*sd*bc03sc*i*alias=pci:v00008086d00000A0Asv*sd*bc03sc*i*alias=pci:v00008086d00000A22sv*sd*bc03sc*i*alias=pci:v00008086d00000A12sv*sd*bc03sc*i*alias=pci:v00008086d00000A02sv*sd*bc03sc*i*alias=pci:v00008086d00000C2Esv*sd*bc03sc*i*alias=pci:v00008086d00000C1Esv*sd*bc03sc*i*alias=pci:v00008086d00000C0Esv*sd*bc03sc*i*alias=pci:v00008086d00000C2Bsv*sd*bc03sc*i*alias=pci:v00008086d00000C1Bsv*sd*bc03sc*i*alias=pci:v00008086d00000C0Bsv*sd*bc03sc*i*alias=pci:v00008086d00000C2Asv*sd*bc03sc*i*alias=pci:v00008086d00000C1Asv*sd*bc03sc*i*alias=pci:v00008086d00000C0Asv*sd*bc03sc*i*alias=pci:v00008086d00000C22sv*sd*bc03sc*i*alias=pci:v00008086d00000C12sv*sd*bc03sc*i*alias=pci:v00008086d00000C02sv*sd*bc03sc*i*alias=pci:v00008086d0000042Esv*sd*bc03sc*i*alias=pci:v00008086d0000041Esv*sd*bc03sc*i*alias=pci:v00008086d0000040Esv*sd*bc03sc*i*alias=pci:v00008086d0000042Bsv*sd*bc03sc*i*alias=pci:v00008086d0000041Bsv*sd*bc03sc*i*alias=pci:v00008086d0000040Bsv*sd*bc03sc*i*alias=pci:v00008086d0000042Asv*sd*bc03sc*i*alias=pci:v00008086d0000041Asv*sd*bc03sc*i*alias=pci:v00008086d0000040Asv*sd*bc03sc*i*alias=pci:v00008086d00000422sv*sd*bc03sc*i*alias=pci:v00008086d00000412sv*sd*bc03sc*i*alias=pci:v00008086d00000402sv*sd*bc03sc*i*alias=pci:v00008086d0000016Asv*sd*bc03sc*i*alias=pci:v00008086d0000015Asv*sd*bc03sc*i*alias=pci:v00008086d00000162sv*sd*bc03sc*i*alias=pci:v00008086d00000152sv*sd*bc03sc*i*alias=pci:v00008086d00000166sv*sd*bc03sc*i*alias=pci:v00008086d00000156sv*sd*bc03sc*i*alias=pci:v00008086d0000016Asv0000152Dsd00008990bc03sc*i*alias=pci:v00008086d00000126sv*sd*bc03sc*i*alias=pci:v00008086d00000116sv*sd*bc03sc*i*alias=pci:v00008086d00000106sv*sd*bc03sc*i*alias=pci:v00008086d0000010Asv*sd*bc03sc*i*alias=pci:v00008086d00000122sv*sd*bc03sc*i*alias=pci:v00008086d00000112sv*sd*bc03sc*i*alias=pci:v00008086d00000102sv*sd*bc03sc*i*alias=pci:v00008086d00000046sv*sd*bc03sc*i*alias=pci:v00008086d00000042sv*sd*bc03sc*i*alias=pci:v00008086d0000A011sv*sd*bc03sc*i*alias=pci:v00008086d0000A001sv*sd*bc03sc*i*alias=pci:v00008086d00002E92sv*sd*bc03sc*i*alias=pci:v00008086d00002E42sv*sd*bc03sc*i*alias=pci:v00008086d00002E32sv*sd*bc03sc*i*alias=pci:v00008086d00002E22sv*sd*bc03sc*i*alias=pci:v00008086d00002E12sv*sd*bc03sc*i*alias=pci:v00008086d00002E02sv*sd*bc03sc*i*alias=pci:v00008086d00002A42sv*sd*bc03sc*i*alias=pci:v00008086d00002A12sv*sd*bc03sc*i*alias=pci:v00008086d00002A02sv*sd*bc03sc*i*alias=pci:v00008086d000029D2sv*sd*bc03sc*i*alias=pci:v00008086d000029C2sv*sd*bc03sc*i*alias=pci:v00008086d000029B2sv*sd*bc03sc*i*alias=pci:v00008086d000029A2sv*sd*bc03sc*i*alias=pci:v00008086d00002992sv*sd*bc03sc*i*alias=pci:v00008086d00002982sv*sd*bc03sc*i*alias=pci:v00008086d00002972sv*sd*bc03sc*i*alias=pci:v00008086d000027AEsv*sd*bc03sc*i*alias=pci:v00008086d000027A2sv*sd*bc03sc*i*alias=pci:v00008086d00002772sv*sd*bc03sc*i*alias=pci:v00008086d00002592sv*sd*bc03sc*i*alias=pci:v00008086d0000258Asv*sd*bc03sc*i*alias=pci:v00008086d00002582sv*sd*bc03sc*i*alias=pci:v00008086d00002572sv*sd*bc03sc*i*alias=pci:v00008086d0000358Esv*sd*bc03sc*i*alias=pci:v00008086d00003582sv*sd*bc03sc*i*alias=pci:v00008086d00002562sv*sd*bc03sc*i*alias=pci:v00008086d00003577sv*sd*bc03sc*i*depends=drm_kms_helper,drm,video,i2c-algo-bitintree=Yvermagic=3.19.0-80-generic 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c__.56619__func__.56387__warned.55739__key.57069__key.57127__key.57128.LC5.LC39i915_gem_object_release_stoleni915_gem_object_get_pages_stoleni915_gem_object_put_pages_stoleni915_gem_object_pin_pages.isra.1.part.2_i915_gem_object_create_stoleni915_gem_object_stolen_ops__func__.53447__print_once.53397__func__.53396__func__.53424__func__.53351__func__.53478__func__.53491__i915_mm_struct_free__worker__i915_mm_struct_freei915_gem_userptr_put_pagesst_set_pageskref_get.part.6i915_gem_userptr_releasei915_gem_userptr_init__mmu_notifieri915_gem_userptr_notifieri915_gem_userptr_dmabuf_exporti915_gem_userptr_get_pages__i915_gem_userptr_get_pages_workercancel_userptri915_gem_userptr_mn_invalidate_range_starti915_gem_userptr_ops__key.56288__i915_error_ok__i915_error_advancei915_error_vprintfi915_error_object_freei915_error_state_freecapture_bo.isra.4i915_error_putsi915_error_object_createi915_gem_record_ringsCSWTCH.227print_error_objprint_error_buffersCSWTCH.189CSWTCH.196__warned.9675__warned.54071__func__.54021warned.54017i915_pipe_enabledi8xx_get_vblank_counter__intel_get_crtc_scanlineibx_irq_resetgen5_gt_irq_resetironlake_irq_resetvlv_display_irq_resetvalleyview_irq_preinstallgen8_gt_irq_resetcherryview_irq_preinstallironlake_irq_uninstalli8xx_irq_preinstalli8xx_irq_uninstalli915_irq_preinstalli915_irq_uninstalli965_irq_preinstalli965_irq_uninstallsnb_update_pm_irqi915_hpd_irq_setuphpd_mask_i915ilk_update_gt_irqibx_irq_pre_postinstallgen5_gt_irq_postinstallibx_irq_postinstallgen8_gt_irq_postinstallgen8_disable_vblankgen8_enable_vblanki915_get_vblank_counter__func__.53577display_pipe_crc_irq_handler__func__.54066i9xx_pipe_crc_irq_handlerhsw_pipe_crc_irq_handlervalleyview_pipestat_irq_handlerCSWTCH.245gen8_irq_postinstallgen8_irq_resetgen8_irq_uninstalli915_get_crtc_scanoutpos__func__.53631semaphore_passedivybridge_parity_work__warned.53862__func__.53892vlv_c0_residencyvlv_get_pipestat_enable_mask.isra.8__warned.53505__warned.53500i915_error_wake_upi915_error_work_func__func__.54443notify_ring.isra.10i8xx_irq_handler__func__.55150snb_gt_irq_handlergm45_get_vblank_counter__func__.53591i915_handle_vblanki915_get_vblank_timestamp__func__.53694intel_hpd_irq_reenable_work__func__.55437i915_digport_work_funci915_hotplug_work_func__func__.53737__func__.53704cpt_irq_handlerhpd_cpt__warned.54011__func__.53999__func__.54269CSWTCH.178CSWTCH.174CSWTCH.176i9xx_hpd_irq_handlerhpd_status_g4xhpd_status_i915i965_irq_handler__func__.55374i915_irq_handler__func__.55248ironlake_enable_vblankironlake_irq_postinstallironlake_disable_vblankgen6_pm_rps_workgen6_rps_irq_handler__func__.54129__warned.54106ironlake_irq_handlerhpd_ibx__func__.54224gen8_gt_irq_handler.isra.16gen8_irq_handlercherryview_irq_handlervalleyview_irq_handleribx_hpd_irq_setup__warned.53475valleyview_display_irqs_installvlv_display_irq_postinstallvalleyview_irq_postinstallcherryview_irq_postinstalli915_enable_vblanki915_enable_asle_pipestati965_irq_postinstalli915_irq_postinstalli8xx_irq_postinstallvalleyview_enable_vblank__warned.53490valleyview_display_irqs_uninstallvlv_display_irq_uninstallvalleyview_irq_uninstallcherryview_irq_uninstalli915_disable_vblankvalleyview_disable_vblanki915_hangcheck_elapsedftrace_define_fields_i915_gem_objectftrace_define_fields_i915_gem_evict_everythingftrace_define_fields_intel_gpu_freq_changeperf_trace_i915_pipe_update_startftrace_raw_event_i915_pipe_update_startftrace_raw_output_i915_pipe_update_startftrace_raw_output_i915_pipe_update_vblank_evadedftrace_raw_output_i915_pipe_update_endftrace_raw_output_i915_gem_object_createftrace_raw_output_i915_vma_bindftrace_raw_output_i915_vma_unbindftrace_raw_output_i915_gem_object_change_domainftrace_raw_output_i915_gem_object_pwriteftrace_raw_output_i915_gem_object_preadftrace_raw_output_i915_gem_object_faultftrace_raw_output_i915_gem_objectftrace_raw_output_i915_gem_evictftrace_raw_output_i915_gem_evict_everythingftrace_raw_output_i915_gem_evict_vmftrace_raw_output_i915_gem_ring_sync_toftrace_raw_output_i915_gem_ring_dispatchftrace_raw_output_i915_gem_ring_flushftrace_raw_output_i915_gem_requestftrace_raw_output_i915_gem_request_completeftrace_raw_output_i915_gem_request_wait_beginftrace_raw_output_i915_ringftrace_raw_output_i915_flip_requestftrace_raw_output_i915_flip_completeftrace_raw_output_i915_reg_rwftrace_raw_output_intel_gpu_freq_changeftrace_raw_output_i915_ppgttftrace_raw_output_i915_contextftrace_raw_output_switch_mmftrace_define_fields_i915_pipe_update_startftrace_define_fields_i915_pipe_update_vblank_evadedftrace_define_fields_i915_pipe_update_endftrace_define_fields_i915_gem_object_createftrace_define_fields_i915_vma_bindftrace_define_fields_i915_vma_unbindftrace_define_fields_i915_gem_object_change_domainftrace_define_fields_i915_gem_object_pwriteftrace_define_fields_i915_gem_object_preadftrace_define_fields_i915_gem_object_faultftrace_define_fields_i915_gem_evictftrace_define_fields_i915_gem_evict_vmftrace_define_fields_i915_gem_ring_sync_toftrace_define_fields_i915_gem_ring_dispat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_event_type_funcs_i915_flip_completeftrace_event_type_funcs_i915_flip_requestftrace_event_type_funcs_i915_ringftrace_event_type_funcs_i915_gem_request_wait_beginftrace_event_type_funcs_i915_gem_request_completeftrace_event_type_funcs_i915_gem_requestftrace_event_type_funcs_i915_gem_ring_flushftrace_event_type_funcs_i915_gem_ring_dispatchftrace_event_type_funcs_i915_gem_ring_sync_toftrace_event_type_funcs_i915_gem_evict_vmftrace_event_type_funcs_i915_gem_evict_everythingftrace_event_type_funcs_i915_gem_evictftrace_event_type_funcs_i915_gem_objectftrace_event_type_funcs_i915_gem_object_faultftrace_event_type_funcs_i915_gem_object_preadftrace_event_type_funcs_i915_gem_object_pwriteftrace_event_type_funcs_i915_gem_object_change_domainftrace_event_type_funcs_i915_vma_unbindftrace_event_type_funcs_i915_vma_bindftrace_event_type_funcs_i915_gem_object_createftrace_event_type_funcs_i915_pipe_update_endftrace_event_type_funcs_i915_pipe_update_vblank_evadedftrace_event_type_funcs_i915_pipe_update_startevent_class_switch_mmevent_class_i915_contextevent_class_i915_ppgttevent_class_intel_gpu_freq_changeevent_class_i915_reg_rwevent_class_i915_flip_completeevent_class_i915_flip_requestevent_class_i915_ringevent_class_i915_gem_requestevent_class_i915_gem_request_wait_beginevent_class_i915_gem_request_completeevent_class_i915_gem_ring_flushevent_class_i915_gem_ring_dispatchevent_class_i915_gem_ring_sync_toevent_class_i915_gem_evict_vmevent_class_i915_gem_evict_everythingevent_class_i915_gem_evictevent_class_i915_gem_objectevent_class_i915_gem_object_faultevent_class_i915_gem_object_preadevent_class_i915_gem_object_pwriteevent_class_i915_gem_object_change_domainevent_class_i915_vma_unbindevent_class_i915_vma_bindevent_class_i915_gem_object_createevent_class_i915_pipe_update_endevent_class_i915_pipe_update_vblank_evadedevent_class_i915_pipe_update_start__tracepoint_ptr_switch_mm__tpstrtab_switch_mm__tracepoint_ptr_i915_context_free__tpstrtab_i915_context_free__tracepoint_ptr_i915_context_create__tpstrtab_i915_context_create__tracepoint_ptr_i915_ppgtt_release__tpstrtab_i915_ppgtt_release__tracepoint_ptr_i915_ppgtt_create__tpstrtab_i915_ppgtt_create__tracepoint_ptr_intel_gpu_freq_change__tpstrtab_intel_gpu_freq_change__tracepoint_ptr_i915_reg_rw__tpstrtab_i915_reg_rw__tracepoint_ptr_i915_flip_complete__tpstrtab_i915_flip_complete__tracepoint_ptr_i915_flip_request__tpstrtab_i915_flip_request__tracepoint_ptr_i915_ring_wait_end__tpstrtab_i915_ring_wait_end__tracepoint_ptr_i915_ring_wait_begin__tpstrtab_i915_ring_wait_begin__tracepoint_ptr_i915_gem_request_wait_end__tpstrtab_i915_gem_request_wait_end__tracepoint_ptr_i915_gem_request_wait_begin__tpstrtab_i915_gem_request_wait_begin__tracepoint_ptr_i915_gem_request_retire__tpstrtab_i915_gem_request_retire__tracepoint_ptr_i915_gem_request_complete__tpstrtab_i915_gem_request_complete__tracepoint_ptr_i915_gem_request_add__tpstrtab_i915_gem_request_add__tracepoint_ptr_i915_gem_ring_flush__tpstrtab_i915_gem_ring_flush__tracepoint_ptr_i915_gem_ring_dispatch__tpstrtab_i915_gem_ring_dispatch__tracepoint_ptr_i915_gem_ring_sync_to__tpstrtab_i915_gem_ring_sync_to__tracepoint_ptr_i915_gem_evict_vm__tpstrtab_i915_gem_evict_vm__tracepoint_ptr_i915_gem_evict_everything__tpstrtab_i915_gem_evict_everything__tracepoint_ptr_i915_gem_evict__tpstrtab_i915_gem_evict__tracepoint_ptr_i915_gem_object_destroy__tpstrtab_i915_gem_object_destroy__tracepoint_ptr_i915_gem_object_clflush__tpstrtab_i915_gem_object_clflush__tracepoint_ptr_i915_gem_object_fault__tpstrtab_i915_gem_object_fault__tracepoint_ptr_i915_gem_object_pread__tpstrtab_i915_gem_object_pread__tracepoint_ptr_i915_gem_object_pwrite__tpstrtab_i915_gem_object_pwrite__tracepoint_ptr_i915_gem_object_change_domain__tpstrtab_i915_gem_object_change_domain__tracepoint_ptr_i915_vma_unbind__tpstrtab_i915_vma_unbind__tracepoint_ptr_i915_vma_bind__tpstrtab_i915_vma_bind__tracepoint_ptr_i915_gem_object_create__tpstrtab_i915_gem_object_create__tracepoint_ptr_i915_pipe_update_end__tpstrtab_i915_pipe_update_end__tracepoint_ptr_i915_pipe_update_vblank_evaded__tpstrtab_i915_pipe_update_vblank_evaded__tracepoint_ptr_i915_pipe_update_start__tpstrtab_i915_pipe_update_startgen8_get_seqnogen8_set_seqnoexeclists_ctx_descriptorexeclists_check_remove_requestgen8_logical_ring_put_irqgen8_logical_ring_get_irqgen8_init_common_ring__func__.53768gen8_init_render_ringintel_lr_context_pin.isra.13execlists_update_contextexeclists_context_unqueuelogical_ring_wait_for_space__func__.53559gen8_emit_bb_startgen8_emit_flush_rendergen8_emit_requestintel_logical_ring_workarounds_emitgen8_emit_flush__func__.53971__func__.54042logical_ring_init__key.53876.LC37ring_write_tailgen6_ring_get_seqnoring_get_seqnoring_set_seqnopc_render_get_seqnopc_render_set_seqnowa_addi9xx_ring_put_irqi9xx_ring_get_irqi8xx_ring_put_irqi8xx_ring_get_irqgen8_ring_put_irqgen8_ring_get_irqgen5_ring_put_irqgen6_ring_put_irqgen5_ring_get_irqgen6_ring_get_irqhsw_vebox_put_irqhsw_vebox_get_irqgen8_emit_pipe_control.part.24gen6_bsd_ring_write_tailstop_ringring_wait_for_spacerender_ring_cleanup__func__.53544CSWTCH.281init_ring_common__func__.53507init_render_ringintel_init_ring_buffer__key.55014__func__.54979i915_dispatch_execbufferi830_dispatch_execbufferi965_dispatch_execbuffergen6_ring_dispatch_execbuffergen8_ring_dispatch_execbufferhsw_ring_dispatch_execbuffergen2_render_ring_flushi9xx_add_requestgen4_render_ring_flushpc_render_add_requestgen6_signalgen6_ring_syncgen6_render_ring_flushgen7_ring_fbc_flushgen7_render_ring_flushgen8_rcs_signalgen8_ring_syncgen6_add_requestbsd_ring_flushgen8_xcs_signalgen6_bsd_ring_flushgen6_ring_flushgen8_render_ring_flushintel_ring_workarounds_emit__gen9_force_wake_put__gen6_gt_wait_for_fifo__vlv_force_wake_get__gen9_force_wake_getg4x_reset_completei915_reset_completeassert_device_not_suspended.isra.6__warned.53312gen6_force_wake_timergen6_gt_check_fifodbg.isra.8__gen6_gt_force_wake_put__vlv_force_wake_put__gen7_gt_force_wake_mt_puthsw_unclaimed_reg_debug.isra.9hsw_unclaimed_reg_detect.isra.13gen8_write32gen8_shadowed_regs__gen6_gt_wait_for_thread_c0.isra.15__gen6_gt_force_wake_get__gen7_gt_force_wake_mt_getgen4_read64gen4_read8gen4_read32gen4_read16gen4_write16gen4_write64gen4_write8gen4_write32gen5_read32gen5_write16gen5_read8gen5_read64gen5_read16gen5_write8gen5_write32gen5_write64gen6_write64gen6_write8gen6_write32gen6_write16gen9_read64gen9_read8gen9_read32gen9_read16chv_read32vlv_read8chv_read16vlv_read16chv_read8chv_read64vlv_read64vlv_read32gen6_read8gen6_read64gen6_read32gen6_read16gen9_write8gen9_shadowed_regsgen9_write64gen9_write16gen9_write32hsw_write32hsw_write16hsw_write64hsw_write8chv_write64chv_write8chv_write32chv_write16gen8_write16gen8_write8gen8_write64__intel_uncore_early_sanitizegen6_null_state_relocsgen6_null_state_batchgen7_null_state_relocsgen7_null_state_batchgen8_null_state_relocsgen8_null_state_batchgen9_null_state_relocsgen9_null_state_batchg4x_audio_codec_disable__func__.53578hsw_audio_codec_disable__func__.53606ilk_audio_codec_disable__func__.53642i915_audio_component_unbindi915_audio_component_bindi915_audio_component_opsi915_audio_component_get_poweri915_audio_component_get_cdclk_freq__warned.53780i915_audio_component_put_poweri915_audio_component_codec_wake_overrideaudio_config_hdmi_pixel_clock.isra.1hdmi_audio_clock__func__.53556hsw_audio_codec_enable__func__.53621ilk_audio_codec_enable__func__.53678g4x_audio_codec_enable__func__.53590__func__.53713i915_audio_component_bind_opsfind_sectionvalidate_vbtfill_detail_timing_dataintel_no_opregion_vbt_callbackintel_no_opregion_vbtpanel_type__func__.53482__func__.53534__func__.53564__func__.53504__func__.53496__func__.53676__func__.53546__func__.53644__func__.53617__func__.53696__func__.53526__arch_hweight32intel_num_dvo_pipesintel_pipe_set_base_atomicintel_update_pipe_sizeironlake_pfit_enablei9xx_crtc_offi945_get_display_clock_speedi915_get_display_clock_speedi9xx_misc_get_display_clock_speedi865_get_display_clock_speedi855_get_display_clock_speedi830_get_display_clock_speedi9xx_update_pll_dividersintel_cpu_transcoder_set_m_nintel_set_pipe_timingsintel_cpu_transcoder_get_m_nintel_default_queue_flipibx_pch_dpll_mode_set__raw_spin_unlock_irqpineview_clocki9xx_clockassert_planes_disabledassert_sprites_disabledchv_clockvlv_clockassert_fdi_rxassert_fdi_txpage_flip_completedvlv_update_cdclk__func__.57004ivb_modeset_global_resources__func__.56160cpt_enable_fdi_bc_bifurcation__func__.56378i9xx_set_pipeconf__func__.57928compute_m_nintel_crtc_update_cursor__warned.58834vlv_prepare_pllivb_manual_fdi_link_trainsnb_b_fdi_train_param__func__.56238gen6_fdi_link_train__func__.56200pipe_dsl_stoppedibx_pch_dpll_enablelpt_disable_clkout_dpintel_framebuffer_init__func__.61131intel_fb_funcsintel_limitintel_limits_pineview_sdvointel_limits_pineview_lvdsintel_limits_i9xx_sdvointel_limits_i9xx_lvdsintel_limits_ironlake_dacintel_limits_ironlake_dual_lvds_100mintel_limits_ironlake_dual_lvdsintel_limits_chvintel_limits_vlvintel_limits_g4x_dual_channel_lvdsintel_limits_g4x_single_channel_lvdsintel_limits_g4x_hdmiintel_limits_g4x_sdvointel_limits_i8xx_dacintel_limits_i8xx_lvdsintel_limits_i8xx_dvointel_limits_ironlake_single_lvds_100mintel_limits_ironlake_single_lvdsdo_intel_finish_page_flip__intel_pageflip_stall_checkquirk_invert_brightnessintel_dmi_reverse_brightnessquirk_backlight_presentquirk_ssc_force_disablequirk_pipeb_forcequirk_pipea_forceintel_gen9_queue_flip__warned.59490__warned.59499intel_gen6_queue_flipintel_gen4_queue_flipintel_gen7_queue_flip__warned.59404valleyview_get_display_clock_speedi915gm_get_display_clock_speedpnv_get_display_clock_speedassert_vblank_disabledskylake_update_primary_plane__func__.55964haswell_crtc_compute_clockintel_plane_destroyintel_mmio_flip_work_funcintel_crtc_cursor_set_obj__func__.58971intel_cursor_plane_update__func__.60750i915_disable_vgaintel_PLL_is_validi9xx_find_best_dpllpnv_find_best_dpllvlv_find_best_dpllchv_find_best_dpllg4x_find_best_dpllironlake_pch_transcoder_set_timings.isra.12hsw_crtc_supports_ips.isra.13ironlake_pfit_disable.isra.15valleyview_calc_cdclk.isra.16intel_get_pipe_timings.isra.25hsw_read_dcompintel_fuzzy_clock_checkintel_pipe_config_compareport_to_power_domain__warned.56919assert_pch_dp_disabledassert_pch_hdmi_disabledassert_pch_transcoder_disabledibx_pch_dpll_disableironlake_get_pfit_config.isra.42haswell_get_pipe_configibx_pch_dpll_get_hw_statei9xx_crtc_clock_get.isra.51__func__.59153hsw_write_dcompintel_user_framebuffer_create_handle__func__.61118drm_gem_object_unreference_unlockedintel_dump_pipe_config.isra.61__func__.59749__func__.59743check_crtc_state__func__.60107intel_gen3_queue_flipintel_gen2_queue_flipintel_cursor_plane_disableupdate_scanline_offsetironlake_get_pipe_configassert_plane.constprop.89assert_cursor.constprop.90assert_dsi_pll.constprop.91lpt_init_pch_refclki9xx_get_pipe_configintel_user_framebuffer_destroyintel_alloc_plane_obj__func__.55716valleyview_modeset_global_resourcescheck_shared_dpll_state__func__.60149intel_crtc_destroyintel_crtc_has_pending_flipintel_disable_pipei9xx_get_plane_config__func__.58053ironlake_get_plane_config__func__.58554i9xx_get_refclk__func__.57649chv_prepare_plli9xx_crtc_compute_clockintel_disable_shared_dpll__func__.55413intel_enable_shared_dpll__func__.55392intel_enable_pipeironlake_pch_enablechv_enable_pll.isra.75vlv_enable_pll.isra.76chv_disable_pllvlv_disable_pllironlake_fdi_link_train__func__.56173i9xx_pfit_enableintel_enable_primary_hw_plane.isra.77intel_disable_primary_hw_plane.isra.78intel_unpin_work_fnintel_pipe_set_basei9xx_update_primary_plane__func__.55818ironlake_update_primary_plane__func__.55914__warned.56334intel_crtc_page_flip__warned.15929__func__.59578intel_primary_plane_disableintel_primary_plane_setplane__func__.60619ironlake_crtc_off__func__.56458ironlake_crtc_compute_clock__func__.58481__func__.58307intel_crtc_enable_planesintel_crtc_load_lutintel_crtc_gamma_setintel_crtc_disable_planesi9xx_crtc_disable__func__.57256ironlake_crtc_disablehaswell_crtc_disable__warned.56930get_crtc_power_domains__intel_set_modeintel_modeset_compute_config__func__.59825__func__.57426__func__.59885__func__.59682__func__.59731__func__.57467i9xx_crtc_enablevalleyview_crtc_enableironlake_crtc_enable__func__.55379haswell_crtc_enable__func__.56361__func__.58199intel_setup_outputs__func__.61020__func__.58739__func__.58745intel_framebuffer_create_for_mode.constprop.88intel_user_framebuffer_create__func__.59222__warned.59539__func__.60065__func__.57385intel_set_modeload_detect_mode__func__.59069__func__.59099intel_crtc_set_config__func__.60505__func__.60394__func__.60479__func__.60417names.60895__func__.61672__func__.61608__func__.61738__func__.61658__func__.61694intel_quirksintel_mode_funcs__compound_literal.0__key.61389intel_primary_formats_gen2intel_primary_plane_funcsintel_cursor_formatsintel_cursor_plane_funcsintel_crtc_funcsintel_primary_formats_gen4intel_helper_funcs__func__.61486__func__.60834.LC175.LC234intel_mark_fb_busy__func__.53334force_audio_namesbroadcast_rgb_namesintel_overlay_recover_from_interruptupdate_polyphase_filtery_static_hcoeffsuv_static_hcoeffscheck_gamma_boundsintel_overlay_do_wait_requestintel_overlay_map_regs.isra.17intel_overlay_release_old_vid_tailintel_overlay_release_old_vidintel_overlay_do_put_image__func__.53434intel_overlay_off_tail__func__.53771intel_psr_exitintel_psr_work__func__.53530__func__.53476aux_msg.53370__key.53668vlv_sideband_rw.constprop.1__func__.53335skl_update_colorkeyskl_get_colorkeyvlv_update_colorkeyvlv_get_colorkeyivb_update_colorkeyivb_get_colorkeyilk_update_colorkeyilk_get_colorkeyintel_post_enable_primaryintel_disable_planeintel_destroy_planeskl_disable_planeskl_update_planeintel_update_primary_plane.isra.3intel_update_plane__func__.53818ivb_disable_planeivb_update_planevlv_disable_planevlv_update_planeilk_disable_planeilk_update_planeilk_plane_formatssnb_plane_formatsintel_plane_funcsvlv_plane_formatsskl_plane_formatsintel_dsm_detectintel_dsm_guid__func__.56917intel_dsm_priv__func__.56906CSWTCH.7CSWTCH.9__func__.56929swsci__print_once.56882__func__.56883asle_work__func__.57014__func__.56991__func__.56986__func__.56996__func__.56954__func__.56981__func__.57000__func__.56976__func__.56971__func__.56966intel_opregion_video_eventsystem_opregion__warned.56918power_state_mapintel_opregion_notifierdescriptor.57054CSWTCH.86descriptor.57066__func__.57112__func__.57123__func__.57055intel_crtc_fb_gamma_setintel_crtc_fb_gamma_getintel_fbdev_set_parintel_fb_initial_config__func__.54550intelfb_allocintelfb_createintelfb_ops__func__.54492intel_fb_helper_funcs__func__.54593intel_fbdev_suspend_worker__func__.54691ch7017_detectch7017_mode_validch7017_destroych7017_read.isra.0ch7017_dump_regs__func__.53423ch7017_get_hw_statech7017_write.isra.1ch7017_dpmsch7017_mode_set__func__.53409ch7017_init__func__.53387ch7xxx_mode_validch7xxx_readb__func__.53394ch7xxx_dump_regs__func__.53449ch7xxx_get_hw_statech7xxx_writeb__func__.53404ch7xxx_detectch7xxx_mode_setch7xxx_destroych7xxx_dpmsch7xxx_initch7xxx_idsch7xxx_dids__func__.53415ivch_detectivch_mode_validivch_read__func__.53370ivch_dump_regsivch_get_hw_stateivch_write__func__.53380ivch_mode_setivch_destroyivch_dpmsivch_init__func__.53388ns2501_detectns2501_destroyns2501_readb__func__.53376ns2501_get_hw_statens2501_writeb__func__.53386ns2501_mode_setregs_1024x768__func__.53411ns2501_mode_valid__func__.53402ns2501_dpms__func__.53430ns2501_initsil164_mode_validsil164_mode_setsil164_readb__func__.53366sil164_dump_regs__func__.53413sil164_get_hw_statesil164_detectsil164_destroysil164_dpmssil164_inittfp410_mode_validtfp410_mode_settfp410_readbtfp410_dump_regs__func__.53419tfp410_get_hw_statetfp410_detecttfp410_getidtfp410_destroytfp410_dpmstfp410_init__func__.53389intel_crt_get_flagsintel_crt_set_dpmsintel_disable_crtintel_enable_crtintel_crt_set_propertyintel_crt_mode_validintel_crt_reset__func__.53983intel_crt_get_hw_stateintel_crt_get_confighsw_crt_post_disable__func__.53687hsw_crt_pre_enablehsw_crt_get_configintel_crt_destroyintel_crt_dpmsintel_no_crt_dmi_callbackintel_crt_compute_config__func__.53743intel_crt_get_edidintel_crt_ddc_get_modesintel_crt_get_modesintel_crt_detect_ddc__func__.53872intel_crt_detect__func__.53931__func__.53848__func__.53766__func__.53788__func__.53898intel_no_crtintel_crt_connector_funcsintel_crt_enc_funcsintel_crt_connector_helper_funcshsw_ddi_pll_disableskl_ddi_pll_disableskl_dpll_regsintel_wait_ddi_buf_idlehsw_ddi_pll_enableskl_ddi_pll_enableintel_ddi_hot_plugintel_ddi_calc_wrpll_linkintel_ddi_get_crtc_encoderhsw_ddi_clock_get.isra.2__func__.54163skl_ddi_pll_get_hw_statehsw_ddi_pll_get_hw_stateintel_disable_ddi__func__.53871intel_ddi_post_disableintel_enable_ddiintel_ddi_compute_configintel_ddi_pre_enablehsw_ddi_translations_dphsw_ddi_translations_hdmihsw_ddi_translations_fdiskl_ddi_translations_dpskl_ddi_translations_hdmibdw_ddi_translations_dpbdw_ddi_translations_hdmibdw_ddi_translations_fdibdw_ddi_translations_edp__func__.53432__func__.53752__func__.53665__func__.54110intel_ddi_funcs__func__.54199intel_hrawclkvlv_pipe_has_pp_onvlv_pipe_has_vdd_onvlv_pipe_anyvlv_initial_pps_pipei9xx_get_aux_clock_dividervlv_get_aux_clock_dividerskl_get_aux_clock_divideri9xx_get_aux_send_ctlskl_get_aux_send_ctlintel_dp_preparepps_lockintel_dp_link_down__func__.55314vlv_post_disable_dp_intel_dp_set_link_trainilk_get_aux_clock_dividerpps_unlockintel_dp_dpcd_read_wakeintel_dp_get_dpcd__func__.55351intel_dp_set_link_trainedp_panel_vdd_schedule_offintel_dp_connector_unregisterintel_dp_set_edidintel_dp_force__func__.55525intel_dp_connector_destroyintel_dp_set_property__func__.55564ilk_post_disable_dpg4x_pre_enable_dp__func__.54257__func__.54494intel_dp_get_config__func__.54619intel_dp_get_hw_state__func__.54580g4x_digital_port_connected.isra.5_pp_ctrl_reg.part.9vlv_power_sequencer_pipeedp_have_panel_vddintel_edp_panel_vdd_sanitize__func__.55587ironlake_get_pp_controledp_panel_vdd_off_sync_pp_stat_reg.part.8__func__.54389vlv_detach_power_sequencer__func__.54773vlv_steal_power_sequencer__func__.54789intel_dp_init_panel_power_sequencerintel_dp_init_panel_power_sequencer_registersvlv_dpllchv_dpll__func__.53702edp_have_panel_power__func__.55760__func__.55683vlv_initial_power_sequencer_setup__func__.53783edp_notify_handleredp_panel_vdd_work_intel_edp_backlight_offintel_dp_probe_oui.part.10__func__.55368intel_dp_probe_mst.part.16__func__.55373intel_dp_get_modesintel_dp_detect_dpcd__func__.55436hsw_get_aux_clock_dividerintel_dp_detect__func__.55511wait_panel_status__func__.54320wait_panel_power_cycle__func__.54344edp_panel_vdd_on__func__.54369intel_dp_aux_ch__func__.53875__func__.54037intel_dp_aux_transferedp_panel_on__func__.54336__func__.54414intel_dp_set_signal_levelsCSWTCH.329__func__.55138__func__.55110__func__.55123__func__.55203intel_dp_update_link_trainCSWTCH.326CSWTCH.325CSWTCH.327_intel_edp_backlight_onintel_edp_backlight_power__func__.54483intel_edp_backlight_on.part.21__func__.54465vlv_enable_dpvlv_dp_pre_pll_enablechv_post_disable_dpchv_dp_pre_pll_enablebws.54191gen4_dpllpch_dpll__func__.54212intel_dp_mode_valid__func__.54448__func__.54340__func__.54476__func__.54522intel_disable_dp__func__.55274__func__.55292intel_dp_check_mst_status__func__.55410intel_enable_dp__func__.54752__func__.54805g4x_enable_dpvlv_pre_enable_dpchv_pre_enable_dp__func__.55388__func__.55429__func__.55616port_mapping.55645__func__.55774intel_dp_connector_funcsintel_dp_connector_helper_funcs__func__.55851__func__.55809__key.55810__func__.55913intel_dp_enc_funcs.LC63intel_dp_mst_enc_get_hw_stateintel_dp_mst_set_propertyintel_mst_best_encoderintel_dp_mst_get_hw_stateintel_dp_mst_hotplugintel_dp_mst_connector_destroyintel_dp_mst_get_modesintel_dp_mst_detectintel_dp_mst_enc_get_configintel_mst_enable_dp__func__.53540intel_mst_pre_enable_dp__func__.53528intel_mst_post_disable_dp__func__.53502intel_mst_disable_dp__func__.53495intel_dp_mst_compute_configintel_dp_mst_encoder_destroyintel_dp_mst_mode_validintel_dp_destroy_mst_connector__func__.53663intel_dp_add_mst_connectorintel_dp_mst_connector_funcsintel_dp_mst_connector_helper_funcsmst_cbsintel_dp_mst_enc_funcsdsi_read_data_returndsi_vc_send_short__func__.53570__func__.53615dsi_vc_write_common__func__.53647.LC36intel_dsi_prepare__func__.53909intel_dsi_destroy__func__.53938intel_dsi_detect__func__.53923intel_dsi_get_config__func__.53849intel_dsi_get_hw_state__func__.53840intel_dsi_post_disable__func__.53811intel_dsi_pre_disable__func__.53789intel_dsi_pre_pll_enable__func__.53913intel_dsi_compute_config__func__.53746intel_dsi_mode_validintel_dsi_enable_nop__func__.53784intel_dsi_hot_plug__func__.53734intel_dsi_get_modesintel_dsi_pre_enable__func__.53756__func__.53780intel_dsi_funcsintel_dsi_devicesintel_dsi_connector_funcsintel_dsi_connector_helper_funcs__func__.53954lfsr_converts__func__.53444__func__.53450__func__.53468generic_mode_validgeneric_mode_fixupgeneric_detectgeneric_get_hw_stategeneric_get_modesgeneric_destroygeneric_exec_sequenceexec_elem__func__.53888seq_namegeneric_disablegeneric_enablegeneric_send_otp_cmdsgeneric_disable_panel_powergeneric_panel_resetgeneric_init__func__.53922mipi_exec_gpiogtable__func__.53874mipi_exec_delaymipi_exec_send_packetintel_dvo_connector_get_hw_stateintel_dvo_get_hw_stateintel_dvo_get_configintel_disable_dvointel_enable_dvointel_dvo_mode_validintel_dvo_pre_enableintel_dvo_get_modesintel_dvo_destroyintel_dvo_detect__func__.53452intel_dvo_dpmsintel_dvo_compute_configintel_dvo_enc_destroyintel_dvo_enc_funcsintel_dvo_devicesintel_dvo_connector_helper_funcsintel_dvo_connector_funcsg4x_infoframe_enabledibx_infoframe_enabledcpt_infoframe_enabledvlv_infoframe_enabledhsw_infoframe_enabledintel_hdmi_preparevlv_enable_hdmiintel_hdmi_pre_enable__func__.54003intel_write_infoframeintel_hdmi_set_avi_infoframeintel_hdmi_set_spd_infoframeintel_hdmi_set_hdmi_infoframeintel_hdmi_get_modesintel_hdmi_set_edidintel_hdmi_force__func__.54034intel_hdmi_detect__func__.54028intel_hdmi_destroyintel_hdmi_set_propertyintel_enable_hdmi__func__.53889intel_hdmi_get_configintel_hdmi_get_hw_stateintel_disable_hdmig4x_infoframe_index__func__.53499g4x_infoframe_enablecpt_write_infoframeibx_write_infoframeg4x_write_infoframevlv_write_infoframehsw_infoframe_enable__func__.53515hsw_write_infoframe__func__.53525chv_hdmi_pre_enableassert_hdmi_port_disabledcpt_set_infoframesibx_set_infoframesg4x_set_infoframeshsw_set_infoframesvlv_set_infoframesintel_hdmi_mode_validvlv_hdmi_post_disablevlv_hdmi_pre_pll_enablechv_hdmi_post_disablechv_hdmi_pre_pll_enablevlv_hdmi_pre_enableintel_hdmi_connector_funcsintel_hdmi_connector_helper_funcsintel_hdmi_enc_funcs.LC14.LC10get_clockget_dataset_clockset_datagmbus_funcgmbus_wait_hw_statusgmbus_xfer_readgmbus_wait_idlegmbus_xfer__func__.53549intel_i2c_quirk_set.part.0intel_gpio_post_xferintel_gpio_pre_xfer__key.53578__key.53579gmbus_portsgmbus_algorithm__func__.53612intel_lvds_mode_validintel_lid_notifyintel_no_modeset_on_lidintel_no_modeset_on_lid_dmi_callbackintel_no_lvds_dmi_callbackintel_dual_link_lvds_callbackintel_lvds_get_modesintel_lvds_get_configintel_lvds_get_hw_stateintel_lvds_compute_config__func__.57255intel_pre_enable_lvdsintel_lvds_destroyintel_lvds_detect__func__.57268intel_enable_lvdsintel_lvds_set_property__func__.57311intel_disable_lvdsintel_no_lvds__func__.57410intel_lvds_connector_funcsintel_lvds_enc_funcsintel_lvds_connector_helper_funcsintel_dual_link_lvdscentre_horizontallycentre_verticallybdw_get_backlightpch_get_backlightbdw_set_backlightpch_set_backlightscaleintel_panel_compute_brightness_vlv_get_backlightvlv_get_backlightvlv_set_backlightintel_panel_actually_set_backlighti9xx_disable_backlighti965_disable_backlightvlv_disable_backlightpch_disable_backlighti9xx_enable_backlight__func__.53681get_backlight_min_vbt__func__.53773vlv_setup_backlightpch_setup_backlightbdw_setup_backlighti965_enable_backlightvlv_enable_backlight__func__.53716bdw_enable_backlight__func__.53654i9xx_get_backlighti9xx_setup_backlighti965_setup_backlighti9xx_set_backlightpch_enable_backlight__func__.53672intel_backlight_device_update_status__func__.53733intel_backlight_device_get_brightness__func__.53542__func__.53645__func__.53724__func__.53873intel_backlight_device_ops__func__.53753intel_sdvo_mode_validintel_sdvo_ddc_proxy_funcintel_sdvo_get_dtd_from_modeintel_sdvo_get_mode_from_dtdintel_sdvo_enc_destroyintel_sdvo_connector_initintel_sdvo_connector_funcsintel_sdvo_connector_helper_funcsintel_sdvo_connector_get_hw_stateintel_sdvo_connector_unregisterintel_sdvo_destroyintel_sdvo_get_analog_edidintel_sdvo_write_sdvox.isra.1intel_sdvo_connector_matches_edid.isra.4__func__.54429intel_sdvo_read_byte.isra.5intel_sdvo_read_responsecmd_status_names__func__.53960intel_sdvo_debug_write.isra.6sdvo_cmd_names__func__.53916intel_sdvo_write_cmd__func__.53932intel_sdvo_ddc_proxy_xferintel_sdvo_enable_hotplugintel_sdvo_get_valueintel_sdvo_get_hw_stateintel_sdvo_create_enhance_property_tv__func__.54690intel_sdvo_create_enhance_property__func__.54700__func__.54713intel_sdvo_get_configCSWTCH.205__func__.54294intel_sdvo_set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