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\_?  ? _?@?@@?@@?@ @? @ 6 f  J   C D   >ލH x, \5 : j&V/ 5e M}s ̄ f jmƐ ae n  R 1a  K {5 L|+[  Fv0 :d W s Aq^Q n<l υ ܂  ς֎ ʌvlv_cmnlane_wasanitize_disable_power_well_optionhsw_set_power_wellskl_set_power_wellintel_power_well_disableintel_power_well_enableskl_disable_dc6skl_enable_dc6bxt_disable_dc9bxt_enable_dc9A0B0C0D0E0F0G0H0I0i915_max_freq_seti915_min_freq_seti915_cache_sharing_seti915_ring_stop_seti915_ring_test_irq_seti915_drop_caches_seti915_error_state_writepipe_crc_set_sourcedisplay_crc_ctl_tokenizedisplay_crc_ctl_parsedisplay_crc_ctl_writepq  /23check_cmdvmap_batchcopy_batchi915_parse_cmdsgen7_render_get_cmd_length_maskgen7_bsd_get_cmd_length_maskgen7_blt_get_cmd_length_maskP@P@hhh """### ##### #$#(#,#0#4#8#<#@#D#H#L#P#T#`#$$$ $ $0$4$8$<$@$RRR RRRRR@RDRHRLRPRTRXR\RRRRR $8       ? ? @?? P?P?@?? @@?? @h ? ?9x:xCxDxExFxGx   ?@@?@ hipqqyz ! @@i915_gem_context_destroy_ioctli915_gem_context_create_ioctldo_switchi915_gem_create_contexti915_gem_context_initi915_gem_execbuffer2i915_gem_execbuffer_relocate_entryeb_lookup_vmasi915_gem_validate_contexti915_gem_do_execbufferi915_gem_execbufferi915_reset_gen7_sol_offsetsi915_gem_ringbuffer_submissionsanitize_enable_ppgttivb_pte_encodesnb_pte_encodeintel_rotate_fb_obj_pagesi915_gem_gtt_initi915_gem_setup_global_gtti915_check_and_clear_faultsi915_ppgtt_init_hwgen6_ppgtt_allocate_page_directoriesgen6_ppgtt_initi915_gem_openi915_gem_initi915_gem_object_bind_to_vmi915_gem_object_set_cache_leveli915_context_is_bannedi915_gem_object_get_pagesi915_gem_mmap_gtti915_gem_object_create_stolen_for_preallocatedi915_pages_create_for_stoleni915_gem_object_create_stoleni915_stolen_to_physicali915_gem_init_stoleni915_setup_compressionABCi915_capture_error_state@intel_hpd_irq_eventi915_hotplug_work_funcivybridge_parity_workintel_hpd_irq_reenable_worki915_get_vblank_timestampi915_get_crtc_scanoutposbxt_hpd_handlergen6_rps_irq_handleribx_irq_handlerpch_get_hpd_pinscpt_irq_handlersnb_gt_irq_handleri8xx_irq_handleri915_irq_handlerdisplay_pipe_crc_irq_handlerintel_hpd_irq_handleri9xx_get_hpd_pinsi965_irq_handleri915_reset_and_wakeup @``  @ @@"dev=%u, ring=%u, ctx=%p, ctx_vm=%p", REC->dev, REC->ring, REC->to, REC->vm"dev=%u, ctx=%p, ctx_vm=%p", REC->dev, REC->ctx, REC->vm"dev=%u, vm=%p", REC->dev, REC->vm"new_freq=%u", REC->freq"%s reg=0x%x, len=%d, val=(0x%x, 0x%x)", REC->write ? "write" : "read", REC->reg, REC->len, (u32)(REC->val & 0xffffffff), (u32)(REC->val >> 32)"plane=%d, obj=%p", REC->plane, REC->obj"plane=%d, obj=%p", REC->plane, REC->obj"dev=%u, ring=%u, seqno=%u, blocking=%s", REC->dev, REC->ring, REC->seqno, REC->blocking ? "yes (NB)" : "no""dev=%u, ring=%u, seqno=%u", REC->dev, REC->ring, REC->seqno"dev=%u, ring=%u, seqno=%u", REC->dev, REC->ring, REC->seqno"dev=%u, ring=%x, invalidate=%04x, flush=%04x", REC->dev, REC->ring, REC->invalidate, REC->flush"dev=%u, ring=%u, seqno=%u, flags=%x", REC->dev, REC->ring, REC->seqno, REC->flags"dev=%u, sync-from=%u, sync-to=%u, seqno=%u", REC->dev, REC->sync_from, REC->sync_to, REC->seqno"dev=%d, vm=%p", REC->dev, REC->vm"dev=%d", REC->dev"dev=%d, size=%d, align=%d %s", REC->dev, REC->size, REC->align, REC->flags & (1<<0) ? ", mappable" : """obj=%p", REC->obj"obj=%p, %s index=%u %s", REC->obj, REC->gtt ? "GTT" : "CPU", REC->index, REC->write ? ", writable" : """obj=%p, offset=%u, len=%u", REC->obj, REC->offset, REC->len"obj=%p, offset=%u, len=%u", REC->obj, REC->offset, REC->len"obj=%p, read=%02x=>%02x, write=%02x=>%02x", REC->obj, REC->read_domains >> 16, REC->read_domains & 0xffff, REC->write_domain >> 16, REC->write_domain & 0xffff"vm=%p, pde=%d, updating %u:%u %s", REC->vm, REC->pde, REC->last, REC->first, __get_str(cur_ptes)"vm=%p, pde=%d (0x%llx-0x%llx)", REC->vm, REC->pde, REC->start, REC->end"vm=%p (%s), 0x%llx-0x%llx", REC->vm, __get_str(name), REC->start, REC->end"obj=%p, offset=%016llx size=%x vm=%p", REC->obj, REC->offset, REC->size, REC->vm"obj=%p, offset=%016llx size=%x%s vm=%p", REC->obj, REC->offset, REC->size, REC->flags & (1<<0) ? ", mappable" : "", REC->vm"obj=%p, size=%u", REC->obj, REC->size"pipe %c, frame=%u, scanline=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline"pipe %c, frame=%u, scanline=%u, min=%u, max=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline, REC->min, REC->max"pipe %c, frame=%u, scanline=%u, min=%u, max=%u", ((REC->pipe) + 'A'), REC->frame, REC->scanline, REC->min, REC->maxpopulate_lr_contextintel_lr_context_deferred_createlrc_setup_wa_ctx_objintel_init_workaround_bbgen8_init_common_ringintel_execlists_submission@ABCAinit_status_pageintel_ring_workarounds_emitinit_ring_commonintel_init_pipe_controlhsw_unclaimed_reg_detectintel_uncore_init0 0 00 xp  0 0 00 i yxaax x xxxxxxyyyxAxx@ xN x""3"xx HH @Z`w@ @Z`w` Z`w @Z`w a `" 1!  `@ `` ` ` ` @` ``!` !1$@~~~~~~~~0$  y1 $,ia yxy0x@1x2x3xxxxxxx!xx x xxx$x@#x`/x x@ x( x""##x`@*x`y{1  yZw .@Zw`.@1!  .`...@1  zix xxx QxxxxxxxPxx xRx0x@1x2x3xyyyyyyyy x x x x xIxJxKxyyy y@y`aayxyy@yyy yxxxy xyyy y xx@@@@ @@@@@ @$@(@,@0@4@8@<@@@D@H@L@P@T@X@\@`@d@h@l@p@t@x@|@C x"" h&x'x(x)x*xx $xOxMx@+x,x-x.x/xx#x`!x{????zix xxx Qxxxxx xxPxx xRx0x@1x2x3xyyyyyyyy x x x x xIxJxKxyyy y@y`aayxyy@yyy yxxxy xyyy y xx@@@@ @@@@@ @$@(@,@0@4@8@<@@@D@H@L@P@T@X@\@`@d@h@l@p@t@x@|@C x""Ux hx$xAOxMx@+x,x-x.x/xx#x!x&x'x(x)x*x{????g4x_audio_codec_enableg4x_audio_codec_disableilk_audio_codec_enableilk_audio_codec_disableaudio_config_hdmi_pixel_clockhsw_audio_codec_enablehsw_audio_codec_disableintel_audio_codec_enableWbpbxii&! "CD parse_ddi_portparse_mipiparse_psrparse_edpparse_driver_featuresparse_device_mappingparse_sdvo_device_mappingparse_sdvo_panel_dataparse_lfp_backlightparse_lfp_panel_dataparse_general_definitionsparse_general_featuresvalidate_vbtinit_vbt_defaultsintel_no_opregion_vbt_callbackLENOVO97027RGintel_sanitize_crtcintel_sanitize_encoderintel_modeset_readout_hw_stateintel_modeset_setup_hw_statei915_redisable_vga_power_onintel_alloc_initial_plane_objintel_setup_outputsintel_check_cursor_planeintel_modeset_stage_output_stateintel_crtc_set_configskl_do_mmio_flipintel_crtc_page_flipintel_crtc_inithaswell_get_pipe_configskylake_get_initial_plane_configlpt_program_iclkiphaswell_crtc_enableskylake_pfit_updatehaswell_crtc_disableironlake_get_initial_plane_configironlake_get_refclkironlake_crtc_compute_clockintel_enable_shared_dpllcpt_set_fdi_bc_bifurcationintel_prepare_shared_dpllintel_disable_shared_dplli9xx_get_initial_plane_configi9xx_pfit_disablei9xx_set_pipeconfironlake_fdi_link_traingen6_fdi_link_trainivb_manual_fdi_link_traincherryview_set_cdclkintel_modeset_initvlv_update_cdclkintel_prepare_plane_fbintel_crtc_restore_modecheck_shared_dpll_statecheck_crtc_statecheck_encoder_stateintel_connector_check_stateintel_decrease_pllclocki9xx_crtc_clock_getintel_release_load_detect_pipeintel_dump_crtc_timingsintel_dump_pipe_configironlake_check_fdi_lanesironlake_fdi_compute_configintel_crtc_compute_configconnected_sink_compute_bppintel_modeset_pipe_configintel_get_load_detect_pipeintel_framebuffer_inithsw_disable_pc8hsw_enable_pc8ironlake_init_pch_refclkskl_set_cdclkbroxton_init_cdclkskl_update_scaler_usersintel_get_shared_dplli9xx_update_cursorskl_plane_ctl_rotationskl_plane_ctl_tilingskl_plane_ctl_formatskl_detach_scalersintel_fb_stride_alignmentintel_pin_and_fence_fb_objintel_tile_heighti9xx_get_refclkNCR CorporationZ!\&!`=j !L @>Ib?H2)>Ib+Hp =[ a0W5O~  *na0W5O~  pna0W5O  8na0W5Ov  pna0W5O  Pn  Ng5p Ng5P@  8kg5h * N8g5h pUg5h P ag5h  N\*Fxb N\*FxP@  a0W @`a0W @`!a0W @`!AR24C8 RG16XR24XB24AR24AB24XR30XB30C8 RG16XR24XB24XR30XB30C8 RG16XR15XR24gen7_fbc_enableilk_fbc_disableilk_fbc_enableg4x_fbc_enableg4x_fbc_disablei8xx_fbc_enablei8xx_fbc_disableintel_fbc_find_crtcintel_fbc_updateintel_fbc_cancel_workintel_increase_pllclockintel_overlay_attrsintel_overlay_continueintel_overlay_put_image0`., h@+@ )`(`>(<9@7 64h`3న@2@1`00000 0@0@/00 .0, 0`+ 0 *` 0ീ( 0@? 0x<`@0 : @008@0x6 0@4` 0@2@ 0@`1 00intel_psr_match_conditionsintel_psr_enablevlv_sideband_rwskl_update_planeintel_check_sprite_planeRG16AB24AR24XB24XR24XB30AB30YUYVYVYUUYVYVYUYXB24XR24YUYVYVYUUYVYVYUYXR24YUYVYVYUUYVYVYUYintel_dsm_platform_mux_infointel_dsm_pci_probeintel_dsm_detects~ONT,swsci_setupasle_isct_stateasle_set_dockingasle_set_convertibleasle_set_button_arrayasle_set_supported_rotation_anglesasle_set_pwm_freqasle_set_pfitasle_set_backlightasle_set_als_illumasle_workintel_opregion_setupintel_didl_outputsswsciintel_fbdev_restore_modeintel_fbdev_init_biosintelfb_createintel_fb_initial_configch7017_initch7017_mode_setch7017_dump_regsch7xxx_initch7xxx_writebch7xxx_readbch7xxx_dump_regsivch_initivch_writeivch_readivch_dump_regsns2501_initns2501_dpmsns2501_mode_validns2501_writebns2501_mode_setns2501_readb @ !"#$%&'~%((pO  12T=$1ds'=#0 12 F =sil164_initsil164_writebsil164_readbsil164_dump_regstfp410_inittfp410_writebtfp410_readbtfp410_dump_regsintel_atomic_setup_scalersintel_atomic_commitintel_atomic_checkintel_plane_atomic_set_propertyintel_plane_atomic_get_propertyintel_plane_atomic_checkintel_crt_resetintel_crt_load_detectintel_crt_detect_ddcvalleyview_crt_detect_hotplugintel_ironlake_crt_detect_hotplugintel_crt_detect_hotplugintel_crt_detecthsw_crt_post_disableintel_crt_get_edidACERZGBDell Inc.XPS 8700intel_ddi_initintel_ddi_get_configbxt_ddi_pll_get_hw_stateintel_ddi_pll_initbxt_ddi_vswing_sequenceintel_ddi_get_hw_statehsw_ddi_pll_selectbxt_ddi_pll_selectskl_ddi_pll_selecthsw_fdi_link_train`@D@`HL``PT44U4@*+MMUM@ffU4NUh@+MtU@fUPp@`00 `@`P@`@`@_  /ˀ_  _  _ _ ϲ oǀ_׀ o o  _  _  _  ___  _ À _׀ intel_dp_get_hw_stateintel_dp_get_configironlake_edp_pll_onironlake_set_pll_cpu_edpvlv_init_panel_power_sequencerintel_enable_dpintel_dp_link_downintel_dp_drrs_initintel_edp_panel_vdd_sanitizeintel_edp_backlight_powerintel_edp_init_connectorintel_dp_check_edpintel_dp_aux_chintel_dp_aux_initvlv_initial_power_sequencer_setupintel_dp_handle_test_requestintel_dp_detect_dpcdintel_dp_detectintel_dp_set_propertyintel_dp_forceintel_dp_init_connectorintel_dp_set_drrs_stateintel_edp_drrs_enable intel_dp_check_link_statusintel_dp_check_mst_statusintel_dp_probe_mstintel_dp_probe_ouiintel_dp_print_ratesintel_dp_get_dpcdintel_dp_hpd_pulseintel_dp_sink_crcintel_dp_complete_link_traingen6_edp_signal_levelsgen7_edp_signal_levelshsw_signal_levelsbxt_signal_levelsintel_dp_set_signal_levelsintel_dp_start_link_trainintel_dp_sink_dpmsintel_edp_backlight_offintel_edp_backlight_onwait_panel_offedp_panel_offwait_panel_onedp_panel_onvlv_power_sequencer_kickintel_dp_init_panel_power_sequencer_registersintel_dp_init_panel_power_sequenceredp_panel_vdd_off_syncvlv_detach_power_sequencervlv_steal_power_sequencervlv_power_sequencer_pipewait_panel_statuswait_panel_power_cycleedp_panel_vdd_onintel_dp_compute_configx`=xK`=x`=xQx   x  intel_mst_disable_dpintel_mst_post_disable_dpintel_mst_pre_enable_dpintel_mst_enable_dpintel_dp_destroy_mst_connectorintel_dsi_hot_plugintel_dsi_compute_configintel_dsi_prepareintel_dsi_pre_pll_enableintel_dsi_enableintel_dsi_device_readyintel_dsi_pre_enableintel_dsi_enable_nopintel_dsi_pre_disableintel_dsi_clear_device_readyintel_dsi_disableintel_dsi_post_disableintel_dsi_get_hw_stateintel_dsi_get_configintel_dsi_connector_destroyintel_dsi_get_modesintel_dsi_mode_validintel_dsi_initvlv_get_dsi_pclkvlv_disable_dsi_pllvlv_configure_dsi_pllvlv_enable_dsi_pllun7y^Wj5bq8G#mipi_exec_send_packetgeneric_exec_sequencevbt_panel_initintel_dvo_detect`8`v`u `8`u@8intel_enable_hdmiintel_hdmi_detectintel_hdmi_forcehsw_infoframe_enablehsw_infoframe_data_regg4x_infoframe_enableg4x_infoframe_indexintel_hdmi_compute_configintel_gmbus_force_bitgmbus_xferP P P P P$PPP P$PPPPP P$Pintel_lvds_detectintel_lvds_set_propertyintel_lvds_compute_configintel_lvds_initApple Inc.MacBookPro6,2Apple Inc.MacBookPro8,2Apple Inc.MacBookPro9,1AppleMacmini1,1AppleMacmini2,1MSIA9830IMSDell Inc.Studio Hybrid 140gDell Inc.OptiPlex FX170AOpeni965GMx-IF AOpen i915GMx-F AOpen i915GMm-HFS AOpen i45GMx-IAO00001JWClientronU800ClientronE830ASUSTeK Computer INC.EB1007 ASUSTeK Computer INC. AT5NM10T-I Hewlett-Packard t5740 Hewlett-Packardhp t5745 Hewlett-Packardhp st5747 MICRO-STAR INTERNATIONAL CO., LTD MS-7469 Gigabyte Technology Co., Ltd. D525TUDSupermicroX7SPA-HFUJITSUESPRIMO Q900 Intel D410PT IntelD425KT IntelD510MO IntelD525MWTOSHIBATECRA A11intel_backlight_device_update_statusintel_panel_get_backlightintel_backlight_device_registerbxt_enable_backlightbdw_enable_backlightpch_enable_backlightvlv_enable_backlighti965_enable_backlightget_backlight_min_vbti9xx_enable_backlightintel_panel_setup_backlightintel_panel_enable_backlightintel_panel_disable_backlightintel_panel_actually_set_backlightintel_sdvo_lvds_initintel_sdvo_analog_initintel_sdvo_create_enhance_property_lvdsintel_sdvo_create_enhance_property_tvintel_sdvo_create_enhance_propertyintel_sdvo_tv_initintel_sdvo_detectintel_sdvo_connector_matches_edidintel_sdvo_get_ddc_modesintel_sdvo_get_lvds_modesintel_sdvo_get_tv_modesintel_sdvo_dvi_initintel_sdvo_output_setupintel_sdvo_get_capabilitiesintel_sdvo_read_byteintel_sdvo_compute_configintel_sdvo_write_infoframeintel_enable_sdvointel_sdvo_read_responseintel_sdvo_debug_writeintel_sdvo_write_cmdintel_sdvo_get_configintel_sdvo_init320x200@@A320x240@@A400x300@&,-LM640x350@B^_~640x400@J640x480@~X704x480@0` 704x576@0r @A`a720x350@?I0^_~720x400@R0720x480@b0720x540@m0<=720x576@xt0@A`a768x576@R{@`@A`a800x600@ !`XYxy832x624@@Apq920x766@C1024x768@C@` !1280x1024@T@` !  !'()*+,}zghijklUVWXYZ^_`[\]abcdefMNO{PQRSTmnopqtuvwxyintel_tv_detect_typeintel_tv_detectintel_tv_compute_configintel_tv_init XP8$ @D|YH" @k@Q$ @D|YH" @k 6$ @D|YH" @k@Q$ @D|YH" @k@AP @L_I"  lq\P @L_I   lqC$@JzY ,,P@[_ 00?@E`P,,q @EPP,,  @EPXkO   @E`Xk  n(E2-EYSM <2-3jd z= v2-3-@  <2-3jd z= q2-3-@ 2-EyOv2-E?S  2-L"V q2-LFZ" <2-3jd z= q2-3-@ 0@5 . .5@0`5.-4@0`@6.-4 0`6. -3 0`70/,30` 8P/,20`8/ , 20`9/+10` :/`+`1 `:+ 1 @;(*0 @`<8 *0 =8)@0@=H`)0@>H)@`@?X(`` (` (`0@5 . .5@0`5.-4@0`@6.-4 0`6. -3 0`70/,30` 8P/,20`8/ , 20`9/+10` :/`+`1 `:+ 1 @;(*0 @`<8 *0 =8)@0@=H`)0@>H)@`@?X(`` (` (`0@6,-@606-,50@7@-,@507-@,40@8.+@408 .+409@.@+30:`.+@3@0:.*3@0@;.@*2@0<.*@20<.)20@=/@)10= /)10>@/(@10@? /@(@11(/(10@6,-@606-,50@7@-,@507-@,40@8.+@408 .+409@.@+30:`.+@3@0:.*3@0@;.@*2@0<.*@20<.)20@=/@)10= /)10>@/(@10@? /@(@11(/(1intel_vgt_deballooni915_getparami915_setparamintel_device_info_runtime_initintel_alloc_mchbar_resourcei915_dump_device_info@dD@AdBdCd @DdEd@!FdGd@Hd Id@ Jd @ Kd @ Ld@ Md@NdOd Qd@Sd@Td(@UdVd@1Wd1XdYdZd0[d0\d @0]d @0^d(0_d @ 0`d@!0ad"0bd#0cd$0dd%ed&0fd 'gd,@(hd,)1id@@*kd+kd,1ld-0md.0nd@/0od@00pd10qd20rd30sd40td50udfailed to re-initialize GPU, declaring wedged! 6[drm] This hardware requires preliminary hardware support. See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support GT register access while GT waking disabled /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.cWARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)))WARN_ON(!IS_HASWELL(dev) && !IS_BROADWELL(dev))WARN_ON(IS_HSW_ULT(dev) || IS_BDW_ULT(dev))WARN_ON(!IS_HSW_ULT(dev) && !IS_BDW_ULT(dev))GEM idle failed, resume might fail DRM not initialized, aborting suspend. failed to load firmware %s (%d) 6[drm] Simulated gpu hang, resetting stop_rings 6[drm] Reset not implemented, but ignoring error for simulated gpu hangs 5drm/i915: Resetting chip after gpu hang timeout waiting for GFX clock force-on (%08x) waiting for GT wells to go %s (%08x) WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL) & mask) != mask)timeout waiting for GT wells to go %s WARN_ON_ONCE(state.event != PM_EVENT_SUSPEND && state.event != PM_EVENT_FREEZE)WARN_ON_ONCE(!(dev_priv->rps.enabled && intel_enable_rc6(dev)))WARN_ON_ONCE(!HAS_RUNTIME_PM(dev))device lock contention, deffering suspend Runtime suspend failed, disabling it (%d) Resume prepare failed: %d, continuing anyway Runtime resume failed, disabling it (%d) User requested overclocking to %d /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_sysfs.cRC6 residency sysfs setup failed RC6p residency sysfs setup failed Media RC6 residency sysfs setup failed l3 parity slice 1 setup failed error_state sysfs setup failed FIFO entries required for mode: %ld Wrong MCH_SSKPD value: 0x%08x This can cause underruns. Enabling RC6 states: RC6 %s RC6p %s RC6pp %s /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_pm.cUnsupported pixel depth for rotationSetting FIFO watermarks - A: %d WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock))WARN_ON(val > dev_priv->rps.max_freq)WARN_ON(val < dev_priv->rps.min_freq)Primary WM%d too large %u (max %u) Sprite WM%d too large %u (max %u) Cursor WM%d too large %u (max %u) Unknown FSB/MEM found, disable CxSR /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.hFIFO watermarks - A: %d, B: %d Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d self-refresh entries: %d, wm: %d self-refresh watermark: display plane %d cursor %d Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d SR watermark: display plane %d, cursor %d display watermark is too large(%d/%ld), disabling cursor watermark is too large(%d/%ld), disabling Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d Setting FIFO watermarks - %c: sprite %c=%d, SR: plane=%d, cursor=%d Setting FIFO watermarks - %c: plane=%d, cursor=%d, SR: plane=%d, cursor=%d timed out waiting for Punit DDR DVFS request %s WM%d latency %u (%u.%u usec) gpu busy, RCS change rejected /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hfmax: %d, fmin: %d, fstart: %d stuck trying to change perf mode warning: pcode (read) mailbox access failed timeout waiting for pcode read (%d) to finish unknown memory frequency 0x%02x WM latency values increased to avoid potential underruns Failed to read display plane latency. Disable CxSR 6[drm] failed to find known CxSR latency (found ddr%s fsb freq %d, mem freq %d), disabling CxSR unexpected fall-through in intel_init_pm warning: pcode (write) mailbox access failed timeout waiting for pcode write (%d) to finish Adjusting RC6 mask to %d (requested %d, valid %d) WARN_ON(!mutex_is_locked(&dev->struct_mutex))BIOS didn't set up PCBR, fixing up RP1(Guar) GPU freq: %d MHz (%u) not enough stolen space for PCTX, disabling RP1(Guar Freq) GPU freq: %d MHz (%u) GT fifo had a previous error %x WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0)current GPU freq: %d MHz (%u) setting GPU freq to %d MHz (%u) WARN_ON(pctx_addr != dev_priv->mm.stolen_base + dev_priv->vlv_pctx->stolen->start)Failed to set the min frequency Overclocking supported. Max: %dMHz, Overclock max: %dMHz Couldn't check for BIOS workaround You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV) Couldn't fix incorrect rc6 voltage WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq)WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq)WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq)WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_runtime_pm.cWARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && state != PUNIT_PWRGT_PWR_GATE(power_well_id))WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe))timeout setting power well state %08x (%08x) WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC)WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D)WARN_ON_ONCE(power_well->data != PIPE_A && power_well->data != PIPE_B && power_well->data != PIPE_C)Display PHY %d is not power up Requesting to disable the power well WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D)Invalid for power well status to be enabled, unless done by the BIOS, when request is to disable! PG1 distributing status timeout PG2 distributing status timeout DC9 already programmed to be enabled. DC5 still not disabled to enable DC9. Platform doesn't support DC9. DC9 already programmed to be disabled. Platform doesn't support DC6. DC6 already programmed to be enabled. DC6 already programmed to be disabled. Disabling display power well support Getting nosync-ref while suspended. WARN_ON(!power_domains->domain_use_count[domain])toggling display PHY side reset 6[drm] RC6 disabled, disabling runtime PM support No CSR support available for this platform Unknown stepping info, firmware loading failed Firmware has wrong CSS header length %u bytes Firmware has wrong package header length %u bytes Firmware not supported for %c stepping Firmware has wrong dmc header length %u bytes Firmware has wrong mmio count %u CSR firmware too big (%u) bytes Memory allocation failed for dmc payload /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_csr.cCSR program storage start is NULL 0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x Frequency requested %d; min hard:%d, soft:%d; max soft:%d, hard:%d VBT: DRRS_type: FIXME: Unrecognized Value crtc_mask: 0x%08x, active: %d, on: %s 0x%X: 0x%08X, mask: 0x%08X, read: 0x%08x, status: %s bit6 swizzle for X-tiling = %s bit6 swizzle for Y-tiling = %s Enabled by kernel parameter: %s WARN_ON(n >= obj->base.size >> PAGE_SHIFT)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_debugfs.cBusy frontbuffer bits: 0x%03x Logical Ring Contexts are disabled Execlist status: 0x%08X, context: %u Read pointer: 0x%08X, write pointer 0x%08X Status buffer %d: 0x%08X, context: %u %s: %u objects, %zu bytes (%zu active, %zu inactive, %zu global, %zu shared, %zu unbound) %pK: %s%s%s%s %8zdKiB %02x %02x [ gtt offset: %08lx, size: %08lx, type: %u)fbcon size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj user size: %d x %d, depth %d, %d bpp, modifier 0x%llx, refcount %d, obj Fence %d, pin count = %d, object = Total %d objects, %zu bytes, %zu GTT size FBC unsupported on this chipset FBC actived, but currently disabled in hardwaredisabled per module param (default off)GPU freq (MHz) Effective CPU freq (MHz) Effective Ring freq (MHz) Hangcheck active, fires in %dms ACTHD = 0x%08llx [current 0x%08llx] PM IER=0x%08x IMR=0x%08x ISR=0x%08x IIR=0x%08x, MASK=0x%08x Lowest (RPN) frequency: %dMHz Nominal (RP1) frequency: %dMHz Max non-overclocked (RP0) frequency: %dMHz Max overclocked frequency: %dMHz efficient (RPe) frequency: %d MHz PUNIT_REG_GPU_FREQ_STS: 0x%08x Master Interrupt Control: %08x Display Engine port interrupt mask: %08x Display Engine port interrupt identity: %08x Display Engine port interrupt enable: %08x Display Engine misc interrupt mask: %08x Display Engine misc interrupt identity: %08x Display Engine misc interrupt enable: %08x North Display Interrupt enable: %08x North Display Interrupt identity: %08x North Display Interrupt mask: %08x South Display Interrupt enable: %08x South Display Interrupt identity: %08x South Display Interrupt mask: %08x Graphics Interrupt enable: %08x Graphics Interrupt identity: %08x Graphics Interrupt mask: %08x Graphics Interrupt mask (%s): %08x %u [%u] objects, %zu [%zu] bytes in gtt %u [%u] active objects, %zu [%zu] bytes %u [%u] inactive objects, %zu [%zu] bytes %u unbound objects, %zu bytes %u purgeable objects, %zu bytes %u pinned mappable objects, %zu bytes %u fault mappable objects, %zu bytes Masking interrupts on rings 0x%08llx Manually setting uncore sharing to %llu Manually setting min freq to %llu Manually setting max freq to %llu Manually setting wedged to %lludpcd read (%zu bytes at %u) failed (%zd) (ringbuffer, space: %d, head: %u, tail: %u, last head: %d)%hu %hu %hu %hu %hu %hu %hu %huid %d:"%s" freq %d clock %d hdisp %d hss %d hse %d htot %d vdisp %d vss %d vse %d vtot %d type 0x%x flags 0x%x CRTC %d: pipe: %c, active=%s (size=%dx%d) fb: %d, pos: %dx%d, size: %dx%d encoder %d: type: %s, connectors: connector %d: type: %s, status: %s cursor visible? %s, position (%d, %d), size %dx%d, addr 0x%08x, active? %s underrun reporting: cpu=%s pch=%s connector %d: type %s, status: %s physical dimensions: %dx%dmm Available Subslice Total: %u Available Subslice Per Slice: %u Available EU Per Subslice: %u Has Subslice Power Gating: %s Enabled Subslice Per Slice: %u Enabled EU Per Subslice: %u Context on %s with no gem object Failed to get pages for context object [0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x No flip due on pipe %c (plane %c) Flip queued on pipe %c (plane %c) Flip pending (waiting for vsync) on pipe %c (plane %c) Flip queued on %s at seqno %x, next seqno %x [current breadcrumb %x], completed? %d Flip not associated with any ring Flip queued on frame %d, (was ready on frame %d), now %d Stall check waiting for page flip ioctl, Current scanout address 0x%08x New framebuffer address 0x%08lx Trying to capture CRC while pipe is off collecting CRCs for pipe %c, %s expected <%lu bytes into pipe crc control too many words, allowed <= %d tokenize failed, a command is %d words Render RC6 residency since boot: %u Media RC6 residency since boot: %u RC information inaccurate because somebody holds a forcewake reference RC6 "Locked to RPn" residency since boot: %u RC6+ residency since boot: %u RC6++ residency since boot: %u CMD: table not sorted ring=%d entry=%d reg=0x%08X prev=0x%08X CMD: Abnormal blt cmd length! 0x%08X CMD: Abnormal bsd cmd length! 0x%08X CMD: Abnormal rcs cmd length! 0x%08X Failed to get space for pages CMD: cmd_parser_init with unknown ring: %d /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_cmd_parser.cCMD: table not sorted ring=%d table=%d entry=%d cmd=0x%08X prev=0x%08X WARN_ON(!hash_empty(ring->cmd_hash))WARN_ON(dest_obj->pages_pin_count == 0)CMD: failed to prepare shadow batch CMD: Failed to set shadow batch to CPU CMD: Failed to vmap shadow batch /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.hCMD: Unrecognized command: 0x%08X CMD: Command length exceeds batch length: 0x%08X length=%u batchlen=%td CMD: Rejected command: 0x%08X CMD: Rejected master-only command: 0x%08X CMD: Rejected register 0x%08X in command: 0x%08X (ring=%d) CMD: Rejected LRM to OACONTROL CMD: Rejected LRM to masked register 0x%08X CMD: Rejected LRI to masked register 0x%08X CMD: Rejected command 0x%08X for bitmask 0x%08X (exp=0x%08X act=0x%08X) (ring=%d) CMD: batch set OACONTROL but did not clear it CMD: Got to the end of the buffer w/o a BBE cmd! WARN_ON(!mutex_is_locked(&pool->dev->struct_mutex))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gem_batch_pool.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gem_context.cFailed to change address space on context switch WARN_ON(dev_priv->ring[RCS].default_context)Disabling HW Contexts; invalid size %d Failed to create default global context (error %ld) %s context support initialized WARN_ON(!dev_priv->ring[RCS].last_context)WARN_ON(dctx->legacy_hw_ctx.rcs_state->active)WARN_ON(i915.enable_execlists)WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gem_render_state.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/asm-generic/dma-mapping-common.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(!list_empty(&vma->exec_list))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gem_evict.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(!mutex_is_locked(&vm->dev->struct_mutex))WARN_ON(!list_empty(&vm->active_list))WARN_ON(i915_gem_evict_vm(vm, false))WARN_ON(n >= obj->base.size >> PAGE_SHIFT)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_ringbuffer.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(entry->flags & __EXEC_OBJECT_NEEDS_MAP && !i915_is_ggtt(vma->vm))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gem_execbuffer.cUnexpected failure to bind target VMA!reloc with multiple write domains: obj %p target %d offset %d read %08x write %08xreloc with read/write non-GPU domains: obj %p target %d offset %d read %08x write %08xRelocation beyond object bounds: obj %p target %d offset %d size %d. Relocation not 4-byte aligned: obj %p target %d offset %d. Impossible case in relocation handling Invalid object handle %d at index %d Object %p [handle %d, index %d] appears more than once in object list execbuf with unknown ring: %d execbuf with non bsd ring but with invalid bsd dispatch flags: %d execbuf with unknown bsd ring: %d execbuf with invalid ring: %d Context %u tried to submit while banned Attempting to use self-modifying batch buffer WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex))clip rectangles are only valid with the render ring clip rectangles are only valid on pre-gen5 UXA submitting garbage DR4, fixing up 0 cliprects but dirt in cliprects fields non-0 rel constants mode on non-RCS rel surface constants mode invalid on gen5+ execbuf with unknown constants: %d Failed to allocate exec list for %d buffers copy %d exec entries failed %d failed to copy %d exec entries back to user (%d) failed to copy %d exec entries back to user PDE #%d mismatch: Actual PDE: %x Expected PDE: %x First entry = %d; Num entries = %d (max=%d) /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gem_gtt.cMissing switch case (%lu) in %s WARN_ON(readq(>t_entries[i-1]) != gen8_pte_encode(addr, level, true))WARN_ON(gtt != vm->pte_encode(addr, level, true, flags))WARN_ON(!ppgtt->pdp.page_directory[pdpe])WARN_ON(pdpe >= GEN8_LEGACY_PDPES)6[drm] applying Ironlake quirks for intel_iommu WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/asm-generic/dma-mapping-common.hWARN_ON(vm->scratch.addr == 0)Created rotated page mapping for object size %lu (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages). Failed to create rotated mapping for object size %lu! (%d) (pitch=%u, height=%u, pixel_format=0x%x, %ux%u tiles, %lu pages) GGTT view %u not implemented! Failed to get pages for GGTT view type %u! Failed to get pages for VMA view type %u (%d)! Failed to map the gtt page table Forced to use aperture for PDEs Allocated pde space (%ldM) at GTT entry: %lx WARN_ON(!ppgtt->pdp.page_directory[i])WARN_ON(start + length < start)WARN_ON(!bitmap_empty(new_pds, GEN8_LEGACY_PDPES))WARN_ON((start + length) > (1ULL << 32))WARN_ON(pt == ppgtt->scratch_pt)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gem_gtt.hWARN_ON(!gen8_pte_count(pd_start, pd_len))WARN_ON(bitmap_empty(pt->used_ptes, GEN6_PTES))WARN_ON(!bitmap_empty(pt->used_ptes, GEN6_PTES))WARN_ON(!bitmap_empty(new_page_tables, I915_PDES))WARN_ON(!list_empty(&ppgtt->base.active_list))WARN_ON(!list_empty(&ppgtt->base.inactive_list))Unexpected fault Addr: 0x%08lx Address space: %s Source ID: %d Type: %d reserving preallocated space: %lx + %zx WARN_ON(i915_gem_obj_ggtt_bound(obj))clearing unused GTT space: [%lx, %lx] /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/drm/drm_mm.h6[drm] Memory usable by graphics device = %zdM 6[drm] VT-d active for gfx access 6[drm] Disabling PPGTT because VT-d is on disabling PPGTT on pre-B3 step VLV WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE))WARN_ON(i915_gem_object_needs_bit17_swizzle(obj))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gem.ccontext hanging too fast, banning! gpu hanging too fast, banning! Timed out waiting for the gpu reset to complete /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/scatterlist.hWARN_ON((gfp & __GFP_DMA32) && (last_pfn >= 0x00100000UL))Attempting to mmap a purgeable buffer Attempting to obtain a purgeable object /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_ringbuffer.h6[drm] BLT not supported on this pre-production hardware; graphics performance will be degraded. WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gem_gtt.hWARN_ON(!ggtt_vma || dev_priv->fence_regs[obj->fence_reg].pin_count > ggtt_vma->pin_count)Failed to initialize GPU, declaring it wedged WARN_ON(!mutex_is_locked(&old->base.dev->struct_mutex))WARN_ON(!(old->frontbuffer_bits & frontbuffer_bits))WARN_ON(!mutex_is_locked(&new->base.dev->struct_mutex))WARN_ON(new->frontbuffer_bits & frontbuffer_bits)WARN_ON(vm == &dev_priv->mm.aliasing_ppgtt->base)%s vma for this object not found. global vma for this object not found. (view=%u) WARN_ON(!i915_gem_obj_ggtt_bound_view(obj, view))WARN_ON(obj->pin_display == 0)bogus fence setup with stride: 0x%x, tiling mode: %i object 0x%08lx not 512K or pot-size 0x%08x aligned object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned WARN_ON((flags & (PIN_MAPPABLE | PIN_GLOBAL)) == PIN_MAPPABLE)WARN_ON(i915_is_ggtt(vm) != !!ggtt_view)WARN_ON(vma->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT)bo is already pinned in %s with incorrect alignment: offset=%lx, req.alignment=%x, req.map_and_fenceable=%d, obj->map_and_fenceable=%d Invalid object (view type=%u) alignment requested %u Attempting to bind an object (view type=%u) larger than the aperture: size=%u > %s aperture=%lu WARN_ON(!i915_gem_valid_gtt_space(vma, obj->cache_level))WARN_ON(flags & (PIN_GLOBAL | PIN_MAPPABLE) && !i915_is_ggtt(vm))WARN_ON(flags & PIN_MAPPABLE && !obj->map_and_fenceable)WARN_ON(obj->frontbuffer_bits)can not change the cache level of pinned objects WARN_ON(!obj->map_and_fenceable)unhandled error in i915_gem_fault: %i &dev_priv->gpu_error.reset_queue/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.h3Unable to purge GPU memory due lock contention. 6Purging GPU memory, %lu bytes freed, %lu bytes still pinned. 3%lu and %lu bytes still available in the bound and unbound GPU page lists. /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gem_stolen.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.h6[drm] Reducing the compressed framebuffer size. This may lead to less power savings than a non-reduced-size. Try to increase stolen memory size if available in BIOS. reserved %d bytes of contiguous stolen space for FBC 6drm: not enough stolen space for compressed buffer (need %d more bytes), disabling. Hint: you may be able to increase stolen memory size in the BIOS to avoid this. 6[drm] DMAR active, disabling use of stolen memory GTT within stolen memory at 0x%llx-0x%llx Stolen memory adjusted to 0x%x-0x%x conflict detected with stolen region: [0x%08x - 0x%08x] found %zd bytes of stolen memory at %08lx WARN_ON(bios_reserved > dev_priv->gtt.stolen_size)creating stolen object: size=%x creating preallocated stolen object: stolen_offset=%x, gtt_offset=%x, size=%x failed to allocate stolen space failed to allocate stolen object failed to allocate stolen GTT space /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hCouldn't read from MCHBAR. Disabling tiling. /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hFailed to allocate memory for bit 17 record /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gem_userptr.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/scatterlist.hWARN_ON(obj->userptr.mm == NULL)WARN_ON(i915_gem_object_put_pages(obj))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_gpu_error.cWARN_ON(n >= obj->base.size >> PAGE_SHIFT)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.hActive process (on ring %s): %s [%d] FAULT_TLB_DATA: 0x%08x 0x%08x SYNC_0: 0x%08x [last synced 0x%08x] SYNC_1: 0x%08x [last synced 0x%08x] SYNC_2: 0x%08x [last synced 0x%08x] %s (w/a) --- gtt_offset = 0x%08x seqno 0x%08x, emitted %ld, tail 0x%08x /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hout of memory, not capturing error state 6[drm] GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace. 6[drm] Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel 6[drm] drm/i915 developers can then reassign to the right component if it's not a kernel issue. 6[drm] The gpu crash dump is required to analyze gpu hangs, so please always attach it. 6[drm] GPU crash dump saved to /sys/class/drm/card%d/error /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_irq.cWARN_ON(enabled_irq_mask & ~interrupt_mask)WARN_ON(!intel_irqs_enabled(dev_priv))WARN_ON(I915_READ(SDEIER) != 0)Interrupt register 0x%x is not zero: 0x%08x WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA)Received HPD interrupt on pin %d although disabled Received HPD interrupt on PIN %d - cnt: 0 HPD interrupt storm detected on PIN %d Received HPD interrupt on PIN %d - cnt: %d trying to get scanoutpos for disabled pipe %c No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx WARN_ON(!dev_priv->l3_parity.which_slice)WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev))Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d. WARN_ON(dev_priv->l3_parity.which_slice)WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV)WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV)Command parser error, iir 0x%08x Command parser error, gt_iir 0x%08x hotplug event received, stat 0x%08x, pins 0x%08x hotplug event received, stat 0x%08x, dig 0x%08x, pins 0x%08x PCH audio power change on port %c Reenabling HPD on connector %s running encoder hotplug functions 6[drm] HPD interrupt storm detected on connector %s: switching from hotplug detection to polling Connector %s (pin %i) received hotplug event. WARN_ON(!mutex_is_locked(&dev->mode_config.mutex))[CONNECTOR:%d:%s] status updated from %s to %s WARN_ON(pm_iir & ~dev_priv->pm_rps_events)Command parser error, pm_iir 0x%08x PCH audio power change on port %d PCH transcoder audio interrupt PCH transcoder CRC done interrupt PCH transcoder CRC error interrupt The master control interrupt lied (GT0)! The master control interrupt lied (GT1)! The master control interrupt lied (GT3)! The master control interrupt lied (PM)! The master control interrupt lied (DE MISC)! hotplug event received, stat 0x%08x The master control interrupt lied (DE PORT)! Fault errors on pipe %c : 0x%08xThe master control interrupt lied (DE PIPE)! The master control interrupt lied (SDE)! WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events)pipe %c: enable_mask=0x%x, status_mask=0x%x 3i915_bpo: render error detected, EIR: 0x%08x 3i915_bpo: INSTDONE_%d: 0x%08x 3i915_bpo: PGTBL_ER: 0x%08x 3i915_bpo: memory refresh error: 3i915_bpo: pipe %c stat: 0x%08x 3i915_bpo: instruction error Hangcheck timer elapsed... %s idle 6[drm] Fake missed irq on %s pipe %c, frame=%u, scanline=%u, min=%u, max=%u pipe %c, frame=%u, scanline=%u obj=%p, offset=%016llx size=%x%s vm=%p obj=%p, offset=%016llx size=%x vm=%p vm=%p, pde=%d (0x%llx-0x%llx) vm=%p, pde=%d, updating %u:%u %s obj=%p, read=%02x=>%02x, write=%02x=>%02x dev=%u, sync-from=%u, sync-to=%u, seqno=%u dev=%u, ring=%u, seqno=%u, flags=%x dev=%u, ring=%x, invalidate=%04x, flush=%04x dev=%u, ring=%u, seqno=%u, blocking=%s %s reg=0x%x, len=%d, val=(0x%x, 0x%x) dev=%u, ring=%u, ctx=%p, ctx_vm=%p /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_lrc.cWARN_ON(!intel_irqs_enabled(dev_priv))WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hWARN_ON(&request->list == &ring->request_list)WARN_ON(lrca & 0xFFFFFFFF00000FFFULL)WARN_ON(n >= obj->base.size >> PAGE_SHIFT)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.hWARN_ON(!intel_irqs_enabled(ring->dev->dev_private))WARN_ON(!i915_gem_obj_is_pinned(ctx_obj0))WARN_ON(!i915_gem_obj_is_pinned(ringbuf0->obj))WARN_ON(!i915_gem_obj_is_pinned(ctx_obj1))WARN_ON(!i915_gem_obj_is_pinned(ringbuf1->obj))WARN_ON(req1 && req1->elsp_submitted)More than 2 already-submitted reqs queued WARN_ON(i915.enable_ppgtt == -1)Lite Restored request removed from queue Preemption without Lite Restore More than two context complete events? non-0 rel constants mode on non-RCS rel surface constants mode invalid on gen5+ execbuf with unknown constants: %d clip rectangles are only valid on pre-gen5 UXA submitting garbage DR4, fixing up 0 cliprects but dirt in cliprects fields /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_ringbuffer.hfailed to quiesce %s whilst cleaning up: %d %s :timed out trying to stop ring WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex))WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0)WARN_ON(ctx->engine[ring->id].pin_count)WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL)WARN_ON(ctx->engine[ring->id].state)WARN_ON(INTEL_INFO(ring->dev)->gen < 8)Alloc LRC backing obj failed. Pin LRC backing obj failed: %d Failed to allocate ringbuffer %s Failed to allocate ringbuffer obj %s: %d Failed to pin and map ringbuffer %s: %d WA batch buffer is not initialized for Gen%d scratch page not allocated for %s alloc LRC WA ctx backing obj failed. pin LRC WA ctx backing obj failed: %d Failed to setup context WA page: %d WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))wa_ctx_bb failed sanity checks: size %d is not aligned to %d WA batch buffer initialization failed: %d Failed get_pages for context obj WARN_ON(idx >= I915_MAX_WA_REGS)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_ringbuffer.cWARN_ON(&request->list == &ring->request_list)WARN_ON(!intel_irqs_enabled(dev_priv))timed out waiting for the BSD ring to wake up %s : timed out trying to stop ring %s head not reset to zero ctl %08x head %08x tail %08x start %08x failed to set %s head to zero ctl %08x head %08x tail %08x start %08x WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0)%s initialization failed [head=%08x], fudging %s: wait for SyncFlush to complete for TLB invalidation timed out %s initialization failed ctl %08x (valid? %d) head %08x tail %08x start %08x [expected %08lx] /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hFailed to allocate seqno page %s pipe control offset: 0x%08x Failed to allocate status page Failed to allocate ringbuffer %s: %d Failed to pin and map ringbuffer %s: %d WARN_ON(wait_mbox == MI_SEMAPHORE_SYNC_INVALID)Failed to allocate semaphore bo. Disabling semaphores Failed to pin semaphore bo. Disabling semaphores WARN_ON(!dev_priv->semaphore_obj)Number of Workarounds emitted: %d failed to quiesce %s whilst cleaning up: %d WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.hWARN_ON(!IS_GEN2(ring->dev) && (I915_READ_MODE(ring) & MODE_IDLE) == 0)WARN_ON(domain->wake_count == 0)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_uncore.cWARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)Unclaimed register detected %s %s register 0x%x Unclaimed register detected, enabling oneshot unclaimed register reporting. Please use i915.mmio_debug=N for more information. GT thread status wait timed out WARN_ON(domain_id >= FW_DOMAIN_ID_COUNT)%s: timed out waiting for forcewake ack to clear. %s: timed out waiting for forcewake ack request. WARN_ON(dev_priv->pm.suspended)Timed out waiting for forcewake timers to finish 6[drm] No MT forcewake available on Ivybridge, this can result in issues 6[drm] when using vblank-synced partial screen updates. WARN_ON(dev_priv->uncore.fw_domains == 0)Missing switch case (%lu) in %s Unclaimed register before interrupt Disable audio codec on pipe %c Disable audio codec on port %c, pipe %c /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_audio.cWARN_ON(acomp->ops || acomp->dev)WARN_ON_ONCE(!HAS_DDI(dev_priv))HDMI audio pixel clock setting for %d not found, falling back to defaults Configuring HDMI audio for pixel clock %d (0x%08x) Enable audio codec on pipe %c, %u bytes ELD Enable audio codec on port %c, pipe %c, %u bytes ELD Enable audio codec, %u bytes ELD ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s] failed to add audio component (%d) Falling back to manually reading VBT from VBIOS ROM for %s BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d BDB_GD too small (%d). Invalid. DRRS supported mode is static DRRS supported mode is seamless DRRS not supported (VBT input) Found panel mode in BIOS VBT tables: LVDS downclock is found in VBT. Normal Clock %dKHz, downclock %dKHz Unsupported backlight data entry size %u PWM backlight not present in VBT (type %u) VBT backlight PWM modulation frequency %u Hz, active %s, min brightness %u, level %u Ignore SDVO panel mode from BIOS VBT tables. Found SDVO panel mode in BIOS VBT tables: No general definition block is found, unable to construct sdvo mapping. different child size is found. Invalid. the SDVO device with slave addr %2x is found on %s port SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d Maybe one SDVO port is shared by two SDVO device. there exists the slave2_addr. Maybe this is a SDVO device with multiple inputs. No SDVO device info is found in VBT No general definition block is found, no devices defined. General definiton block child device size is too small. no child dev is parsed from VBT No memory space for child device No eDP BDB found but eDP panel supported. VBT has unknown eDP link rate value %u VBT has unknown eDP lane count value %u VBT has unknown eDP pre-emphasis value %u VBT has unknown eDP voltage swing value %u VBT has unknown PSR lines to wait %u Found MIPI Config block, panel index = %d No MIPI Sequence found, parsing complete Sequence start is beyond sequence block size, corrupted sequence block Corrupted sequence/size, bailing out Sequence elements going beyond block itself. Sequence block parsing failed MIPI related vbt parsing complete More than one child device for port %c in VBT. Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d Internal DP port %c is TMDS compatible Analog port %c is also DP or TMDS compatible Port %c is not DP/TMDS/CRT compatible Unexpected DDC pin for port B Unexpected DDC pin for port C Unexpected DDC pin for port D Unexpected AUX channel for port A Unexpected AUX channel for port B Unexpected AUX channel for port C Unexpected AUX channel for port D VBT HDMI level shift for port %c: %d Sequence block detected but no valid configuration WARN_ON(clock->n == 0 || clock->p == 0)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_display.cWARN_ON(clock->n + 2 == 0 || clock->p == 0)Current CD clock rate: %d kHz WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE)WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE)plane %c assertion failure, should be disabled but not plane %c assertion failure, should be off on pipe %c but is still active plane %d assertion failure, should be off on pipe %c but is still active sprite %c assertion failure, should be off on pipe %c but is still active FDI RX state assertion failure (expected %s, current %s) PCH DP (0x%08x) enabled on transcoder %c, should be disabled IBX PCH dp port still using transcoder B FDI TX state assertion failure (expected %s, current %s) Invalid cursor width/stride, width=%u, stride=%u Missing switch case (%lu) in %s FDI_RX_IIR before link train 0x%x FDI train 1 fail on vswing %d FDI train 2 fail on vswing %d WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))) PCH refclk assertion failure, should be active but is disabled [CRTC:%d]%s config %p for pipe %c fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u crtc timings: %d %d %d %d %d %d %d %d %d, type: 0x%x flags: 0x%x num_scalers: %d, scaler_users: 0x%x, scaler_id: %d gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x pch pfit: pos: 0x%08x, size: 0x%08x, %s ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x ddi_pll_sel: %u; dpll_hw_state: ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, fp0: 0x%x, fp1: 0x%x %s PLANE:%d plane: %u.%u idx: %d disabled, scaler_id = %d %s PLANE:%d plane: %u.%u idx: %d enabled FB:%d, fb = %ux%u format = 0x%x scaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u mismatch in DDB state pipe %c plane %d (expected (%u,%u), found (%u,%u)) mismatch in DDB state pipe %c cursor (expected (%u,%u), found (%u,%u)) 6[drm] applying inverted panel brightness quirk 6[drm] Backlight polarity reversed on %s 6[drm] applying backlight present quirk 6[drm] applying lvds SSC disable quirk 6[drm] applying pipe b force quirk 6[drm] applying pipe a force quirk unknown plane in flip command Unknown pnv display core clock 0x%04x WARN_ON(drm_crtc_vblank_get(crtc) == 0) Cursor dimension %dx%d not supported PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled IBX PCH hdmi port still using transcoder B WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex))Couldn't get view from plane state!mismatch in cpu_transcoder (expected %i, found %i) mismatch in has_pch_encoder (expected %i, found %i) mismatch in fdi_lanes (expected %i, found %i) mismatch in fdi_m_n.gmch_m (expected %i, found %i) mismatch in fdi_m_n.gmch_n (expected %i, found %i) mismatch in fdi_m_n.link_m (expected %i, found %i) mismatch in fdi_m_n.link_n (expected %i, found %i) mismatch in fdi_m_n.tu (expected %i, found %i) mismatch in has_dp_encoder (expected %i, found %i) mismatch in dp_m_n.gmch_m (expected %i, found %i) mismatch in dp_m_n.gmch_n (expected %i, found %i) mismatch in dp_m_n.link_m (expected %i, found %i) mismatch in dp_m_n.link_n (expected %i, found %i) mismatch in dp_m_n.tu (expected %i, found %i) mismatch in dp_m2_n2.gmch_m (expected %i, found %i) mismatch in dp_m2_n2.gmch_n (expected %i, found %i) mismatch in dp_m2_n2.link_m (expected %i, found %i) mismatch in dp_m2_n2.link_n (expected %i, found %i) mismatch in dp_m2_n2.tu (expected %i, found %i) mismatch in dp_m_n.gmch_m (expected %i or %i, found %i) mismatch in dp_m_n.gmch_n (expected %i or %i, found %i) mismatch in dp_m_n.link_m (expected %i or %i, found %i) mismatch in dp_m_n.link_n (expected %i or %i, found %i) mismatch in dp_m_n.tu (expected %i or %i, found %i) mismatch in base.adjusted_mode.crtc_hdisplay (expected %i, found %i) mismatch in base.adjusted_mode.crtc_htotal (expected %i, found %i) mismatch in base.adjusted_mode.crtc_hblank_start (expected %i, found %i) mismatch in base.adjusted_mode.crtc_hblank_end (expected %i, found %i) mismatch in base.adjusted_mode.crtc_hsync_start (expected %i, found %i) mismatch in base.adjusted_mode.crtc_hsync_end (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vdisplay (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vtotal (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vblank_start (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vblank_end (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vsync_start (expected %i, found %i) mismatch in base.adjusted_mode.crtc_vsync_end (expected %i, found %i) mismatch in pixel_multiplier (expected %i, found %i) mismatch in has_hdmi_sink (expected %i, found %i) mismatch in limited_color_range (expected %i, found %i) mismatch in has_infoframe (expected %i, found %i) mismatch in has_audio (expected %i, found %i) mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_INTERLACE) (expected %i, found %i) mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_PHSYNC) (expected %i, found %i) mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_NHSYNC) (expected %i, found %i) mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_PVSYNC) (expected %i, found %i) mismatch in base.adjusted_mode.flags(DRM_MODE_FLAG_NVSYNC) (expected %i, found %i) mismatch in pipe_src_w (expected %i, found %i) mismatch in pipe_src_h (expected %i, found %i) mismatch in gmch_pfit.control (expected %i, found %i) mismatch in gmch_pfit.pgm_ratios (expected %i, found %i) mismatch in gmch_pfit.lvds_border_bits (expected %i, found %i) mismatch in pch_pfit.enabled (expected %i, found %i) mismatch in pch_pfit.pos (expected %i, found %i) mismatch in pch_pfit.size (expected %i, found %i) mismatch in scaler_state.scaler_id (expected %i, found %i) mismatch in ips_enabled (expected %i, found %i) mismatch in double_wide (expected %i, found %i) mismatch in ddi_pll_sel (expected 0x%08x, found 0x%08x) mismatch in shared_dpll (expected %i, found %i) mismatch in dpll_hw_state.dpll (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.dpll_md (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.fp0 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.fp1 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.wrpll (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.ctrl1 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.cfgcr1 (expected 0x%08x, found 0x%08x) mismatch in dpll_hw_state.cfgcr2 (expected 0x%08x, found 0x%08x) mismatch in pipe_bpp (expected %i, found %i) mismatch in base.adjusted_mode.crtc_clock (expected %i, found %i) mismatch in port_clock (expected %i, found %i) active crtc, but not enabled in sw tracking crtc's computed active state doesn't match tracked active state (expected %i, found %i) crtc's computed enabled state doesn't match tracked enabled state (expected %i, found %i) crtc active state doesn't match with hw state (expected %i, found %i) WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != PF_PIPE_SEL_IVB(crtc->pipe))Unknown DPLL mode %08x in programmed mode transcoder assertion failed, should be off on pipe %c but is still active unknown pipe linked to edp transcoder WARN_ON(!pll->get_hw_state(dev_priv, pll, &pipe_config->dpll_hw_state))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hStaged freeing scaler id %d.%d from %s:%d crtc_state = %p scaler_users = 0x%x %s:%d scaler_user index %u.%u: src %ux%u dst %ux%u size is out of scaler range PLANE:%d scaling %ux%u->%ux%u not allowed with colorkeyPLANE:%d FB:%d unsupported scaling format 0x%x %s:%d staged scaling request for %ux%u->%ux%u crtc_state = %p scaler_users = 0x%x WARN_ON(intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE)FDI mPHY reset assert timeout FDI mPHY reset de-assert timeout plane %c assertion failure (expected %s, current %s) cursor on pipe %c assertion failure (expected %s, current %s) DSI PLL state assertion failure (expected %s, current %s) /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_drv.hWARN_ON(!intel_fb->obj->framebuffer_references--)WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.hmore active pll users than references: %i vs %i pll in active use but not on in sw tracking pll in on but not on in use in sw tracking pll on state mismatch (expected %i, found %i) pll active crtcs mismatch (expected %i, found %i) pll enabled crtcs mismatch (expected %i, found %i) WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->cdclk_freq)WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND)timed out waiting for CDclk change WARN_ON(!crtc_state->base.state)using SSC reference clock of %d kHz Couldn't find PLL settings for mode! PLL state assertion failure (expected %s, current %s) asserting DPLL %s with no DPLL %s assertion failure (expected %s, current %s) WARN_ON(pll->config.crtc_mask == 0)disable %s (active %d, on? %d) for crtc %d PCH VGA enabled on transcoder %c, should be disabled PCH LVDS enabled on transcoder %c, should be disabled failed to disable transcoder %c enable %s (active %d, on? %d) for crtc %d FDI RX PLL assertion failure (expected %s, current %s) FDI TX PLL assertion failure, should be active but is disabled WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)))panel assertion failure, pipe %c regs locked failed to enable transcoder %c pipe %c assertion failure (expected %s, current %s) WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE)disabling pfit, current: 0x%08x timed out waiting for port %c ready: got 0x%x, expected 0x%x 128-bit pixels are not supported for display!pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x WARN_ON(!mutex_is_locked(&dev->struct_mutex))Y tiling bo slipped through, driver bug! flip queue: previous flip completed, continuing flip queue: crtc already busy /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_ringbuffer.hWARN_ON(intel_fb_obj(old_fb) == NULL)tiling_mode doesn't match fb modifier Unsupported fb modifier 0x%llx! pitch (%d) must be at least %u byte aligned %s pitch (%u) must be at less than %d pitch (%d) must match tiling stride (%d) WARN_ON(__i915_wait_request(mmio_flip->req, mmio_flip->crtc->reset_counter, false, NULL, &mmio_flip->i915->rps.mmioflips))CRTC:%d Disabled scaler id %u.%u WARN_ON(x != src_x || y != src_y)WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue))WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, !intel_crtc_has_pending_flip(crtc), 60*HZ) == 0)CRTC:%d using pre-allocated %s WARN_ON(pll->new_config->crtc_mask)CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d) failed to find PLL for pipe %c WARN_ON(crtc->config->scaler_state.scaler_id < 0)Requesting pfit without getting a scaler first for crtc_state = %p scaler_id = %d Failed to disable PCH transcoder WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000))Timed out waiting for IPS enable WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0))Timed out waiting for IPS disable WARN_ON(pll->new_config == &pll->config)WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc))PCode CDCLK freq change notify failed (err %d, freq %d) PCode CDCLK freq set failed, (err %d, freq %d) timout waiting for DE PLL unlock timeout waiting for DE PLL lock failed to inform PCU about cdclk change rejecting invalid cloning configuration WARN_ON(!connector_state->crtc)rejecting conflicting digital port configuration [CONNECTOR:%d:%s] checking for sink bpp constrains clamping display bpp (was %d) to EDID reported max of %d clamping display bpp (was %d) to default limit of 24 checking fdi config on pipe %c, lanes %i invalid fdi lane config on pipe %c: %i lanes only 2 lanes on haswell, required: %i lanes invalid shared fdi lane config on pipe %c: %i lanes only 2 lanes on pipe %c: required %i lanes fdi link B uses too many lanes to enable link C fdi link bw constraint, reducing pipe bpp to %i intel_crtc = %p drm_state (pipe_config->base.state) = %p loop in pipe configuration computation CRTC bw constrained, retrying plane bpp: %i, pipe bpp: %i, dithering: %i WARN_ON(!pll->config.crtc_mask)mode set failed: pipe %c stuck WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & ~SBI_SSCDIVINTPHASE_DIVSEL_MASK)iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x Failed to enable PCH transcoder has_panel %d has_lvds %d has_ck505 %d D_COMP RCOMP still in progress Switching back to LCPLL failed Kicking stuck page flip: queued at %d, now %d active connector not linked to encoder encoder->connectors_active not set encoder active on the wrong pipe connector's staged encoder doesn't match current encoder encoder's stage crtc doesn't match current crtc encoder's active_connectors set, but no crtc encoder's enabled state mismatch (expected %i, found %i) encoder's computed active state doesn't match tracked active state (expected %i, found %i) encoder's hw state doesn't match sw tracking (expected %i, found %i) active encoder's pipe doesn't match(expected %i, found %i) [CONNECTOR:%d:%s], [ENCODER:%d:%s] no pipe available for load-detect creating tmp fb for load-detection reusing fbdev for load-detection framebuffer failed to allocate framebuffer for load-detection failed to set mode on load-detect pipe Couldn't release load detect pipe. [CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i) [CONNECTOR:%d:%s] to [NOCRTC] [CONNECTOR:%d:%s] to [CRTC:%d] failed to set mode on [CRTC:%d], err = %d WARN_ON(!set->fb && (set->num_connectors != 0))WARN_ON(set->fb && (set->num_connectors == 0))FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i [CRTC:%d] mode restore failed, out of memoryFailed to add [CONNECTOR:%d:%s] to state: %ld Failed to add [CRTC:%d] to state: %ld WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex))Something enabled VGA plane, disabling it [CRTC:%d] hw state readout: %s %s hw state readout: crtc_mask 0x%08x, on %i [ENCODER:%d:%s] hw state readout: %s, pipe %c [CONNECTOR:%d:%s] hw state readout: %s [ENCODER:%d:%s] has active connectors but no active pipe! [ENCODER:%d:%s] manually disabled [CRTC:%d] wrong plane connection detected! [CRTC:%d] hw state adjusted, was %s, now %s WARN_ON(encoder->connectors_active)%s enabled but not in use, disabling swapping pipes & planes for FBC WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe)pipe %c sprite %c init failed: %d failed to pin boot fb on pipe %d enabled FBC, pitch %d, yoff %d, plane %c cancelling pending FBC enable fbc disabled per module param more than one pipe active, disabling compression mode incompatible with compression, disabling mode too large for compression, disabling plane not A, disabling compression framebuffer not tiled or fenced, disabling compression Rotation unsupported, disabling framebuffer too large, disabling compression disabling active FBC for update Failed to allocate FBC work structure unsupported config, disabling FBC /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_fifo_underrun.cuncleared fifo underrun on pipe %c uncleared pch fifo underrun on pch transcoder %c PCH transcoder %c FIFO underrun WARN_ON(!mutex_is_locked(&dev->struct_mutex))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_frontbuffer.c/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.h/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_overlay.cWARN_ON(overlay->last_flip_req)WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_drv.hWARN_ON(!mutex_is_locked(&dev->struct_mutex))WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex))WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE))buffer used for overlay image can not be tiled failed to attach phys overlay regs failed to pin overlay register bo failed to move overlay register bo into the GTT 6[drm] initialized overlay support WARN_ON(dev_priv->overlay->active)Overlay, status: 0x%08x, interrupt: 0x%08x WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_psr.cWARN_ON(!(val & EDP_PSR_ENABLE))Timed out waiting for PSR Idle for re-enable PSR not supported on this platform PSR not supported by this panel WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex))WARN_ON(!drm_modeset_is_locked(&crtc->mutex))PSR condition failed: Stereo 3D is Enabled PSR condition failed: Interlaced is Enabled PSR condition failed: Link Standby requested/needed but not supported on this platform WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe))Timed out waiting for PSR Idle State PSR transition took longer than expected WARN_ON(!mutex_is_locked(&dev_priv->sb_lock))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_sideband.cIOSF sideband idle wait (%s) timed out IOSF sideband finish wait (%s) timed out WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock))DPIO read pipe %c reg 0x%x == 0x%x timeout waiting for SBI to become ready timeout waiting for SBI to complete read transaction timeout waiting for SBI to complete write transaction Unsuitable framebuffer for plane /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_sprite.cHorizontal scaling factor out of limits Vertical scaling factor out of limits Source dimensions exceed hardware limits WARN_ON(src->x1 < (int) state->base.src_x || src->y1 < (int) state->base.src_y || src->x2 > (int) state->base.src_x + state->base.src_w || src->y2 > (int) state->base.src_y + state->base.src_h)plane = %d PS_PLANE_SEL(plane) = 0x%x WARN_ON(drm_crtc_vblank_get(&crtc->base))Potential atomic update failure on pipe %c Atomic update failure on pipe %c (start=%u end=%u) colorkey not allowed with scaler no _DSM method for intel device VGA switcheroo: detected DSM switching method %s handle 6[drm] ACPI BIOS requests an excessive sleep of %u ms, using %u ms instead SWSCI request already in progress No request on ASLC interrupt 0x%08x opregion backlight request ignored updating opregion backlight %d/255 Button array event is not supported (nothing) Button array event is not supported (rotation lock) Button array event is not supported (volume down) Button array event is not supported (volume up) Button array event is not supported (windows) Button array event is not supported (power) Convertible is not supported (clamshell) Convertible is not supported (slate) Docking is not supported (docked) Docking is not supported (undocked) unsupported intel_encoder type %d /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_opregion.c4i915_bpo: No ACPI video bus found More than 8 outputs detected via ACPI More than 8 outputs in connector list graphic opregion physical addr: 0x%x Public ACPI methods supported SWSCI BIOS requested (%08x) SBCB callbacks that are not supported (%08x) SWSCI GBDA callbacks %08x, SBCB callbacks %08x connector %s not enabled, skipping connector %s is disabled by user, skipping /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_fbdev.cconnector %s has no encoder or crtc, skipping fallback: cloned configuration looking for cmdline mode on connector %s looking for preferred mode on connector %s %d using first mode listed on connector %s looking for current mode on connector %s connector %s on pipe %c [CRTC:%d]: %dx%d%s fallback: Not all outputs enabled Not using firmware configuration failed to allocate framebuffer /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/include/linux/kref.hBIOS fb too small (%dx%d), we require (%dx%d), releasing it no BIOS fb, allocating a new one allocated %dx%d fb: 0x%08lx, bo %p WARN_ON(INTEL_INFO(dev)->num_pipes == 0)pipe %c not active or no fb, skipping found possible fb from plane %c no active fbs found, not using BIOS config checking plane %c for BIOS fb fb not wide enough for plane %c (%d vs %d) pipe %c area: %dx%d, bpp: %d, size: %d fb not big enough for plane %c (%d vs %d) fb big enough for plane %c (%d >= %d) BIOS fb not suitable for all pipes, not using re-used BIOS config but lost an fb on crtc %d using BIOS fb for initial console WARN_ON(state != FBINFO_STATE_RUNNING)CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT: %02x CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT: %02x CH7017_VERTICAL_ACTIVE_LINE_OUTPUT: %02x CH7017_ACTIVE_INPUT_LINE_OUTPUT: %02x CH7017_LVDS_PLL_VCO_CONTROL: %02x CH7017_LVDS_PLL_FEEDBACK_DIV: %02x Registers before mode setting ch701x not detected, got %d: from %s slave %d. Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. ch7xxx not detected; got 0x%02x from %s slave %d. Detected %s chipset, vendor/device ID 0x%02x/0x%02x Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. ivch detect failed due to address mismatch (%d vs %d) Unable to read register 0x%02x from %s:0x%02x. Unable to write register 0x%02x to %s:%d set mode (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d). Detailed requested mode settings are: clock : %d kHz hdisplay : %d hblank start : %d hblank end : %d hsync start : %d hsync end : %d htotal : %d hskew : %d vdisplay : %d vblank start : %d hblank end : %d vsync start : %d vsync end : %d vtotal : %d is mode valid (hdisplay=%d,htotal=%d,vdisplay=%d,vtotal=%d) Trying set the dpms of the DVO to %i ns2501 not detected got %d: from %s Slave %d. init ns2501 dvo controller successfully! Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. sil164 not detected got %d: from %s Slave %d. init sil164 dvo controller successfully! Unable to read register 0x%02x from %s:%02x. Unable to write register 0x%02x to %s:%d. tfp410 not detected got VID %X: from %s Slave %d. tfp410 not detected got DID %X: from %s Slave %d. i915 does not yet support async commit /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_atomic.ccrtc_state = %p need = %d avail = %d scaler_users = 0x%x Too many scaling requests %d > %d Failed to add [PLANE:%d] to drm_state WARN_ON(intel_plane->pipe != intel_crtc->pipe)Attached scaler id %u.%u to %s:%d i915 only support atomic plane operations on a single CRTC at the moment i915 only supports atomic plane operations at the moment Y/Yf tiling required for 90/270! Unsupported pixel format %s for 90/270! /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_atomic_plane.cWARN_ON(!(val & SPLL_PLL_ENABLE))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_crt.c6[drm] Skipping CRT initialization for %s CRT GMBUS EDID read failed, retry using GPIO bit-banging CRT detected via DDC:0x50 [EDID] CRT not detected via DDC:0x50 [EDID reports a digital panel] CRT not detected via DDC:0x50 [no valid EDID found] trigger hotplug detect cycle: adpa=0x%x timed out waiting for FORCE_TRIGGERironlake hotplug adpa=0x%x, result %d valleyview hotplug adpa=0x%x, result %d timed out waiting for FORCE_DETECT to go off/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_ddi.clane stagger config different for lane 01 (%08x) and 23 (%08x) No pipe for ddi port %c found compute_config() on unknown output! %d encoders on crtc for pipe %c Timeout waiting for DDI BUF %c idle bit timeout during PHY%d power on WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL)FDI link training done on step %d pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp No valid values found for the given pixel clock failed to find PLL for pipe %c no PLL dividers found for clock %d pipe %c Invalid encoder type %d for pipe %c Vswing programming not done for encoder %d ddi translation table missing WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE)VBT says port %c is not DVI/HDMI/DP compatible, respect it DP training pattern 3 not supported /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_dp.cWARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)Refresh rate should be positive non-zero. DRRS: intel_crtc not initialized Only Seamless DRRS supported. DRRS requested for previously set RR...ignoring eDP encoder disabled. CRTC not Active eDP Refresh Rate set to : %dHz dp port still on, should be off 160MHz cpu eDP clock, might need ilk devA w/a pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp No pipe for dp port 0x%x found invalid max DP link bw val %x, using 1.62Gbps VDD left on by BIOS, adjusting state tracking WARN_ON(intel_dp->want_panel_vdd)PP_STATUS: 0x%08x PP_CONTROL: 0x%08x detaching pipe %c power sequencer from port %c WARN_ON(pipe != PIPE_A && pipe != PIPE_B)stealing pipe %c power sequencer from port %c stealing pipe %c power sequencer from active eDP port %c picked pipe %c power sequencer for port %c skipping pipe %c power seqeuncer kick due to port %c being active kicking pipe %c power sequencer for port %c panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d panel power up delay %d, power down delay %d, power cycle delay %d backlight on delay %d, off delay %d no initial power sequencer for port %c initial power sequencer for port %c: pipe %c WARN_ON(k >= DP_MAX_SUPPORTED_RATES)Broken DP branch device, ignoring Could not read test request from sink Could not write test response to sink CP or sink specific irq unhandled mask %08x value %08x status %08x control %08x Panel status timeout: status %08x control %08x eDP port %c panel power wasn't enabled eDP powered off while attempting aux channel communication. WARN_ON(send_bytes > 20 || recv_size > 20)dp aux hw did not signal timeout (has irq: %i)! dp_aux_ch not done status 0x%08x dp_aux_ch receive error status 0x%08x dp_aux_ch timeout status 0x%08x dp_aux_ch not started status 0x%08x Turn eDP port %c panel power on eDP port %c panel power already on Unsupported voltage swing/pre-emph level Unsupported voltage swing/pre-emphasis level:0x%x /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_drv.hpanel power control backlight %s DP link computation with max lane count %i max bw %d pixel clock %iKHz clamping bpp for eDP panel to BIOS-provided %i DP link bw %02x lane count %d clock %d bpp %d DP link bw required %i available %i eDP port %c VDD already requested on Turn eDP port %c panel power off Need eDP port %c VDD to turn off panel Wait for panel power off time failed to %s sink power state failed to enable link training too many full retries, give up too many voltage retries, give up failed to update link training failed to start channel equalization Channel EQ done. DP Training successful Timed out waiting for DP idle patterns channel EQ not ok, retraining failed to get ESI - device may have failed ignoring long hpd on eDP port %c WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex))WARN_ON(!intel_encoder->base.crtc)Test request in short pulse not handled %s: channel EQ not ok, retraining MST device may have disappeared %d vs %d initializing pipe %c power sequencer for port %c Panel is unable to calculate CRC after 6 vblanks Adding %s connector on port %c drm_dp_aux_register() for %s failed (%d) sysfs_create_link() for %s failed (%d) 6[drm] failed to retrieve link info, disabling eDP DRRS supported for Gen7 and above Downclock mode is not found. DRRS not supported seamless DRRS supported for eDP panel. using pipe %c for initial backlight setup WARN_ON(IS_VALLEYVIEW(dev) && is_edp(intel_dp) && port != PORT_B && port != PORT_C)Timed out waiting for ACT sent Same special packet %02x twice in a row. Video mode command 0x%08x send failed. Timeout waiting for HS/LP DATA FIFO !full Timeout waiting for HS/LP CTRL FIFO !full Timeout waiting for read data. Unsupported Mipi device to reg basebpp match assertion failure (expected %d, current %d) /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_dsi_pll.cUnsupported MIPI element, skipping sequence execution Generic Read not yet implemented or used DCS Read not yet implemented or used Burst mode freq is less than computed Values crossing maximum limits, restricting to max values Dual link: DSI_DUAL_LINK_FRONT_BACK Dual link: DSI_DUAL_LINK_PIXEL_ALT WARN_ON(!intel_crtc->config->has_hdmi_sink)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_hdmi.cEnabling HDMI audio on pipe %c picking bpc to 8 for HDMI output forcing pipe bpc to %i for HDMI too high HDMI clock, rejecting mode Writing DIP with CTL reg disabled HDMI port enabled, expecting disabled /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_drv.hGMBUS [%s] timed out waiting for idle GMBUS [%s] timed out after NAK GMBUS [%s] NAK for addr: %04x %c(%d) GMBUS [%s] NAK on first message, retry 6[drm] GMBUS [%s] timed out, falling back to bit banging on pin %d WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_i2c.c%sabling bit-banging on %s. force bit now %d 6[drm] Skipping forced modeset for %s 6[drm] Skipping LVDS initialization for %s 6[drm] Forcing lvds to dual link mode on %s forcing display bpp (was %d) to LVDS (%d) timed out waiting for panel to power on timed out waiting for panel to power off using preferred mode from EDID: LVDS downclock is found in EDID. Normal clock %dKhz, downclock %dKhz detected %s-link lvds configuration lid notifier registration failed No LVDS modes found, disabling. Apple Mac Mini (Core 2 series)WARN_ON(source_min > source_max)/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_panel.cWARN_ON(target_min > target_max)WARN_ON(panel->backlight.max == 0)WARN_ON(pipe != PIPE_A && pipe != PIPE_B)clamping VBT min backlight %d/255 to %d/255 pch backlight already enabled cpu backlight already enabled updating intel_backlight, brightness=%d/%d Skipping backlight disable on vga switch no backlight present per VBT, but present per quirk failed to setup backlight for connector %s Connector %s backlight initialized, %s, brightness %u/%u WARN_ON(panel->backlight.device)Failed to register backlight: %ld Connector %s backlight sysfs interface registered connector_is_digital? %d, monitor_is_digital? %d /build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/intel_sdvo.ch_overscan: max %d, default %d, current %d v_overscan: max %d, default %d, current %d hpos: max %d, default %d, current %d vpos: max %d, default %d, current %d saturation: max %d, default %d, current %d contrast: max %d, default %d, current %d hue: max %d, default %d, current %d sharpness: max %d, default %d, current %d brightness: max %d, default %d, current %d flicker_filter: max %d, default %d, current %d flicker_filter_adaptive: max %d, default %d, current %d flicker_filter_2d: max %d, default %d, current %d tv_chroma_filter: max %d, default %d, current %d tv_luma_filter: max %d, default %d, current %d SDVO pixel multiplier mismatch, port: %i, encoder: %i First %s output reported failure to sync SDVO TV clock out of range: %i writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i 6[drm] Setting output timings on %s failed 6[drm] Setting input timings on %s failed unknown pixel multiplier specified initialising analog device %d SDVO capabilities: vendor_id: %d device_id: %d device_rev_id: %d sdvo_version_major: %d sdvo_version_minor: %d sdvo_inputs_mask: %d smooth_scaling: %d sharp_scaling: %d up_scaling: %d down_scaling: %d stall_support: %d output_flags: %d %s: Unknown SDVO output type (0x%02x%02x) SDVO output failed to setup on %s %s device VID/DID: %02X:%02X.%02X, clock range %dMHz - %dMHz, input 1: %c, input 2: %c, output 1: %c, output 2: %c SDVO_CMD_GET_ATTACHED_DISPLAYSSDVO_CMD_GET_INTERRUPT_EVENT_SOURCESDVO_CMD_GET_INPUT_TIMINGS_PART1SDVO_CMD_GET_INPUT_TIMINGS_PART2SDVO_CMD_SET_INPUT_TIMINGS_PART1SDVO_CMD_SET_INPUT_TIMINGS_PART2SDVO_CMD_SET_OUTPUT_TIMINGS_PART1SDVO_CMD_SET_OUTPUT_TIMINGS_PART2SDVO_CMD_GET_OUTPUT_TIMINGS_PART1SDVO_CMD_GET_OUTPUT_TIMINGS_PART2SDVO_CMD_CREATE_PREFERRED_INPUT_TIMINGSDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGESDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGESDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTSSDVO_CMD_GET_SUPPORTED_TV_FORMATSSDVO_CMD_GET_SUPPORTED_POWER_STATESSDVO_CMD_SET_ENCODER_POWER_STATESDVO_CMD_SET_DISPLAY_POWER_STATESDVO_CMD_SET_CONTROL_BUS_SWITCHSDVO_CMD_GET_SDTV_RESOLUTION_SUPPORTSDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORTSDVO_CMD_GET_SUPPORTED_ENHANCEMENTSSDVO_CMD_GET_MAX_FLICKER_FILTERSDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVESDVO_CMD_GET_FLICKER_FILTER_ADAPTIVESDVO_CMD_SET_FLICKER_FILTER_ADAPTIVESDVO_CMD_GET_MAX_FLICKER_FILTER_2DSDVO_CMD_GET_FLICKER_FILTER_2DSDVO_CMD_SET_FLICKER_FILTER_2DSDVO_CMD_GET_MAX_TV_CHROMA_FILTERSDVO_CMD_GET_MAX_TV_LUMA_FILTERSDVO_CMD_GET_AUDIO_ENCRYPT_PREFERDetected Composite TV connection Detected S-Video TV connection Detected Component TV connection Integrated TV is not present. 6[drm] balloon space: range [ 0x%lx - 0x%lx ] %lu KiB. 6[drm] VGT interface version mismatch! 6[drm] Virtual GPU for Intel GVT-g detected. 6[drm] VGT ballooning configuration: 6[drm] Mappable graphic memory: base 0x%lx size %ldKiB 6[drm] Unmappable graphic memory: base 0x%lx size %ldKiB Invalid ballooning configuration! 6[drm] VGT balloon successfully 6[drm] Display disabled (module parameter) 6[drm] Display fused off, disabling has subslice power gating: %s &dev_priv->modeset_restore_locki915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags=%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s6[drm] This is an early pre-production Haswell machine. It may not be fully functional. failed to remove conflicting framebuffer drivers 6[drm] Replacing VGA console driver failed to remove conflicting VGA console Failed to create our workqueue. Failed to create our dp workqueue. Failed to create our hangcheck workqueue. 6[drm] failed to find VBIOS tables WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier))/build/linux-lts-vivid-PmeBs4/linux-lts-vivid-3.19.0/ubuntu/i915/i915_dma.c/`,/`,,/`/`/`,/`/`/`/`/`/`/`/`/`,,/`,,/`,,/`/`/`,,,, /`/`/`/`/`//``/`//`/`//```,,.-/`/`/`/`/`/`/`/`/`/`/`/`//``/`/`/`/`/`/`/`/`/`/`,,,,,,,,,,,/`/`/`,,,,,,,,,,///``/``,,,,,,,,,,,,,/`/`,/`,,,,,,,,,,././,,,,,,,,,,,,,,,,,,,,//``timeout disabling GT waking Found Ibex Peak PCH WARN_ON(!IS_GEN5(dev))Found CougarPoint PCH Found PantherPoint PCH Found LynxPoint PCH Found LynxPoint LP PCH Found SunrisePoint PCH WARN_ON(!IS_SKYLAKE(dev))Found SunrisePoint LP PCH No PCH found. Failed to reset chip: %i Failed hw init on reset %d offSuspend complete failed: %d dev: %p Suspending device Device suspended Resuming device Device resumed KMS and UMS disabled. i915_bpoIntel Graphics20150522Resetting error state %d %x bogus CZ count value%u l3 parity sysfs setup failed RPS sysfs setup failed errorgt_RPn_freq_mhzgt_RP1_freq_mhzgt_RP0_freq_mhzvlv_rpe_freq_mhzgt_min_freq_mhzgt_max_freq_mhzgt_cur_freq_mhzgt_act_freq_mhzl3_parity_slice_1l3_paritymedia_rc6_residency_msrc6pp_residency_msrc6p_residency_msrc6_residency_msrc6_enableBAFIFO size - (0x%08x) %s: %d FIFO watermark level: %ld primaryspritePipe %c %s %c FIFO size: %d flush pipe %c (pass %d) onoffEnabling RC6 states: RC6 %s Latency value missing Pixel clock is zero! Pixel size is zero! enableddisabledmemory self-refresh is %s self-refresh entries: %d SR latency is 0, disabling DSPFW1 register is %x DSPFW3 register is %x WARN_ON(wm_lp != 1)WARN_ON(!r->enable)WARN_ON(p->pixel_rate == 0)WARN_ON(!wm_changed)%s WM%d latency not provided ips_link_to_i915_driverWARN_ON(!dev_priv->vlv_pctx)bad pxval: %ld SKL Mailbox read error = %d 32unknown fsb frequency 0x%04x Gen9 PlanePrimarySpriteCursorOdd GPU freq value PCBR: 0x%08x DDR speed: %d MHz max GPU freq: %d MHz (%u) RPe GPU freq: %d MHz (%u) min GPU freq: %d MHz (%u) Odd GPU freq values yesnoGPLL not enabled GPLL enabled? %s GPU status: 0x%08x 6[drm] RC6 %s &dev_priv->rps.hw_lockenabling %s disabling %s WARN_ON(ctrl != state)WARN_ON(ctrl << 16 != state)Enabling power well Timeout enabling power well PG1 in disabled state Unknown power well %lu Enabling %s Disabling %s PG0 not enabled %s enable timeout Power well on. Interrupts not disabled yet. Enabling DC9 DC5 still not disabled. Disabling DC9 Backlight is not disabled. Enabling DC6 Runtime PM not enabled. Disabling DC6 &power_domains->lockDevice still suspended. WARN_ON(!power_well->count)always-onpower well 1power well 2MISC IO power wellDDI A/E power wellDDI B power wellDDI C power wellDDI D power welldisplaydpio-common-bcdpio-common-ddpio-tx-b-01dpio-tx-b-23dpio-tx-c-01dpio-tx-c-23dpio-commoni915/skl_dmc_ver1.binCSR is not loaded. CSR SSP Base Not fine CSR HTP Not fine yesnoLLC: %s eLLC: %zuMB Current sequence (%s): %x gen: %d pch: %d is_mobile: %s is_i85x: %s is_i915g: %s is_i945gm: %s is_g33: %s need_gfx_hws: %s is_g4x: %s is_pineview: %s is_broadwater: %s is_crestline: %s is_ivybridge: %s is_valleyview: %s is_haswell: %s is_skylake: %s is_preliminary: %s has_fbc: %s has_pipe_cxsr: %s has_hotplug: %s cursor_needs_physical: %s has_overlay: %s overlay_needs_physical: %s supports_tv: %s has_llc: %s has_ddi: %s has_fpga_dbg: %s %c %s , activeRPS enabled? %d GPU busy? %d CPU waiting? %d %s [%d]: %d boosts%s Semaphore boosts: %d%s MMIO flip boosts: %d%s Kernel boosts: %d not supported GPU idle: %s IRQs disabled: %s No active crtc found CRTC %d: eDP: DSI: HDMI: DP: Other encoder (id=%d). VBT: DRRS_type: Static VBT: DRRS_type: Seamless VBT: DRRS_type: None DRRS Supported: Yes Idleness DRRS: Disabled Busy_frontbuffer_bits: 0x%X DRRS_State: DRRS_HIGH_RR DRRS_State: DRRS_LOW_RR DRRS_State: Unknown(%d) Vrefresh: %d DRRS Supported : No SizeEndStart%-15s%8s%8s%8s Pipe %c Cursor %-13s%8u%8u%8u Plane%-8d%8u%8u%8u DPLL%i: %s, id: %i tracked hardware state: dpll: 0x%08x dpll_md: 0x%08x fp0: 0x%08x fp1: 0x%08x wrpll: 0x%08x %s requests: %d %x @ %d: %s [%d] No requests OKFAILWorkarounds applied: %d %llubugDDC = 0x%08x DDC2 = 0x%08x C0DRB3 = 0x%04x C1DRB3 = 0x%04x MAD_DIMM_C0 = 0x%08x MAD_DIMM_C1 = 0x%08x MAD_DIMM_C2 = 0x%08x TILECTL = 0x%08x GAMTARBMODE = 0x%08x ARB_MODE = 0x%08x DISP_ARB_CTL = 0x%08x L-shaped memory detected enableddisabledself-refresh: %s Currently: unknown Currently: enabled Currently: disabled Semaphores are disabled %s Last signal:0x%08llx (0x%02llx) 0x%08x Sync seqno: 0x%08x Last wait: PIPE_APIPE_BPIPE_CPIPE_A_PANEL_FITTERPIPE_B_PANEL_FITTERPIPE_C_PANEL_FITTERTRANSCODER_ATRANSCODER_BTRANSCODER_CTRANSCODER_EDPPORT_DDI_A_2_LANESPORT_DDI_A_4_LANESPORT_DDI_B_2_LANESPORT_DDI_B_4_LANESPORT_DDI_C_2_LANESPORT_DDI_C_4_LANESPORT_DDI_D_2_LANESPORT_DDI_D_4_LANESPORT_DDI_E_2_LANESPORT_DSIPORT_CRTPORT_OTHERVGAAUDIOPLLSAUX_AAUX_BAUX_CAUX_DINITUse countPower well/domain%-25s %s %-25s %d %-23s %d nonexisting DP port %c %02x%02x%02x%02x%02x%02x PSR not supported Sink_Support: %s Source_OK: %s Enabled: %s Active: %s Re-enable work scheduled: %s HW Enabled & Active bit: %s pipe %cPerformance_Counter: %u PDP%d 0x%016llx GFX_MODE: 0x%08x PP_DIR_BASE: 0x%08x PP_DIR_BASE_READ: 0x%08x PP_DIR_DCLV: 0x%08x aliasing PPGTT: pd gtt offset: 0x%08x ECOCHK: 0x%08x proc: %s Status pointer: 0x%08X %d requests in queue Head request id: %u Head request tail: %u [k]batch poolg XYp* purgeable dirty%x ] %x %x%s%s%s (name: %d) (pinned x %d) (display) (fence: %d) (pp (g (stolen: %08lx) (%s mappable) (%s) (frontbuffer: 0x%03x)%s cache[%d]: %d objects total: %d Reserved fences = %d Total fences = %d unusedActive: Inactive: FBC enabled FBC disabled: unsupported by this chipsetno outputsnot enough stolen memorymode not supportedmode too largeFBC unsupported on planescanout buffer not tiledmultiple pipes are enableddisabled per chip defaultunknown reasonunsupported on this chipset %d %d %d GMCH temp: %ld Chipset power: %ld GFX power: %ld Total power: %ld Hangcheck disabled Hangcheck inactive %s: seqno = %x [current %x] max ACTHD = 0x%08llx score = %d action = %d Requested P-state: %d Requested VID: %d Current VID: %d Current P-state: %d GT_PERF_STATUS: 0x%08x Render p-state ratio: %d Render p-state VID: %d Render p-state limit: %d RPSTAT1: 0x%08x RPMODECTL: 0x%08x RPINCLIMIT: 0x%08x RPDECLIMIT: 0x%08x RPNSWREQ: %dMHz CAGF: %dMHz RP CUR UP EI: %dus RP CUR UP: %dus RP PREV UP: %dus Up threshold: %d%% RP CUR DOWN EI: %dus RP CUR DOWN: %dus RP PREV DOWN: %dus Down threshold: %d%% Current freq: %d MHz Actual freq: %d MHz Idle freq: %d MHz Min freq: %d MHz Max freq: %d MHz DDR freq: %d MHz actual GPU freq: %d MHz current GPU freq: %d MHz max GPU freq: %d MHz min GPU freq: %d MHz idle GPU freq: %d MHz no P-state info available Display IER: %08x Display IIR: %08x Display IIR_RW: %08x Display IMR: %08x Port hotplug: %08x DPFLIPSTAT: %08x DPINVGTT: %08x Pipe %c stat: %08x GT Interrupt IMR %d: %08x GT Interrupt IIR %d: %08x GT Interrupt IER %d: %08x PCU interrupt mask: %08x PCU interrupt identity: %08x PCU interrupt enable: %08x Pipe %c power disabled Pipe %c IMR: %08x Pipe %c IIR: %08x Pipe %c IER: %08x Master IER: %08x Render IER: %08x Render IIR: %08x Render IMR: %08x PM IER: %08x PM IIR: %08x PM IMR: %08x Interrupt enable: %08x Interrupt identity: %08x Interrupt mask: %08x Pipe %c stat: %08x Stolen: %u objects, %zu bytes %zu [%lu] gtt total %llu 0x%llx 0x%08llx WM%d %u (%u.%u usec) Stopping rings 0x%08llx Resetting error state Dropping caches: 0x%08llx WARN_ON(size > sizeof(buf))%04x: %*ph no ppgtt for context %d default context: context %d: HW context (default context %s) %s: CRTC info --------- Connector info -------------- primary plane disabled , mode: name: %s subpixel order: %s CEA rev: %d DPCD rev: %x audio support: %s fixed mode: modes: SSEU Device Info Available Slice Total: %u Available EU Total: %u Has Slice Power Gating: %s Has EU Power Gating: %s SSEU Device Status Enabled Slice Total: %u Enabled Subslice Total: %u Enabled EU Total: %u CONTEXT: %s %u Not bound in GGTT WARN_ON(page == NULL)%s.wake_count = %u Stall check enabled, %d prepares MMIO update completed? %d WARN_ON(!IS_G4X(dev))stopping CRCs for pipe %c pipeunknown object %s unknown pipe %s unknown source %s UpDownVideo Turbo Mode: %s HW control enabled: %s SW control enabled: %s RC6 Enabled: %s Render Power Well: %s Media Power Well: %s RC information accurate: %s RC1e Enabled: %s Deep RC6 Enabled: %s Deepest RC6 Enabled: %s Current RC state: Core Power Down on RC3 RC6 RC7 Unknown Core Power Down: %s RC6 residency since boot: %u RC6 voltage: %dmV RC6+ voltage: %dmV RC6++ voltage: %dmV HD boost: %s Boost freq: %d Gated voltage change: %s Starting frequency: P%d Max P-state: P%d Min P-state: P%d RS1 VID: %d RS2 VID: %d Render standby enabled: %s Current RS state: RC1 RC1E RS1 RS2 (RC6) RC3 (RC6+) unknown Turbo enabled: %s %8u %8x %8x %8x %8x %8x &pipe_crc->wqi915_forcewake_useri915_dpcdnonebit9bit9/bit10bit9/bit11bit9/bit10/bit11unknownbit9/bit17bit9/bit10/bit17i915_wedgedi915_max_freqi915_min_freqi915_cache_sharingi915_ring_stopi915_ring_missed_irqi915_ring_test_irqi915_gem_drop_cachesi915_error_statei915_next_seqnoi915_display_crc_ctli915_pri_wm_latencyi915_spr_wm_latencyi915_cur_wm_latencyi915_fbc_false_colori915_capabilitiesi915_gem_objectsi915_gem_gtti915_gem_pinnedi915_gem_activei915_gem_inactivei915_gem_stoleni915_gem_pageflipi915_gem_requesti915_gem_seqnoi915_gem_fence_regsi915_gem_interrupti915_gem_hwsi915_gem_hws_blti915_gem_hws_bsdi915_gem_hws_veboxi915_gem_batch_pooli915_frequency_infoi915_hangcheck_infoi915_drpc_infoi915_emon_statusi915_ring_freq_tablei915_fbc_statusi915_ips_statusi915_sr_statusi915_opregioni915_gem_framebufferi915_context_statusi915_dump_lrci915_execlistsi915_forcewake_domainsi915_swizzle_infoi915_ppgtt_infoi915_llci915_edp_psr_statusi915_sink_crc_eDP1i915_energy_uJi915_pc8_statusi915_power_domain_infoi915_display_infoi915_semaphore_statusi915_shared_dplls_infoi915_dp_mst_infoi915_wa_registersi915_ddb_infoi915_sseu_statusi915_drrs_statusi915_rps_boost_infoplane1plane2pfTVDP-BDP-CDP-Dautoi915_pipe_A_crci915_pipe_B_crci915_pipe_C_crcFailed to vmap pages CMD: cmd_parser_init failed! CMD: Failed to vmap batch CMD: Failed to copy batch L3 remapping failed ring init context: %d WARN_ON(ret)Couldn't pin %d PPGTT setup failed (%ld) fakeLRHWHW context %d created HW context %d destroyed WARN_ON(ring->id != RCS)only %d relocs resolved i915_bpoWARN_ON(i915_vma_unbind(vma))Failed to lookup VMA execbuf with %d buffers Could not create LRC %u: %d execbuf with %u cliprects no rel constants on pre-gen4 sol reset is gen7/rcs only Bad box %d,%d..%d,%d %s didn't clear reload execbuf2 with %d buffers dirty rvsd2 field PDE: %x 0x%lx [%03d,%04d]: = %08x SCRATCH WARN_ON(!pd->page_table[pde])WARN_ON(!pt->page)failed to set up gmch Scratch setup failed Unknown GMADR size (%lx) Adding PPGTT at offset %x WARN_ON(!pd->page_table[i])WARN_ON(!pd)WARN_ON(!pt)WARN_ON(upper_32_bits(start))GGTTPPGTTCouldn't idle GPU Reservation failed: %i GMADR size = %ldM GTT stolen size = %zdM ppgtt mode: %i WARN_ON(!view)GPWARN_ON(flags == 0)IRQs disabledWARN_ON(!ring->irq_get(ring))WARN_ON(request == NULL)WARN_ON(ret != -EIO)no view specifiedWARN_ON(vma->node.allocated)WARN_ON(dev_priv->mm.busy)PPGTT enable failed %d Context enable failed %d allow wake ack timed out globalppgttWARN_ON(vma->pin_count == 0)WARN_ON(fence->pin_count)ggttmappabletotalWARN_ON(!ggtt_view)WARN_ON(ret == -ERESTARTSYS)WARN_ON(i915_vma_unbind(vma))WARN_ON(obj->pages_pin_count)WARN_ON(!ctx)i915_gem_objecti915_gem_vmai915_gem_request&dev_priv->pending_flip_queue&dev_priv->fb_tracking.lockoffset=0x%x, size=%d Graphics Stolen MemoryWARN_ON(size == 0)WARN_ON(size & 4095)WARN_ON(stolen_offset & 4095)unknown tiling mode WARN_ON(ret && ret != -EIO)&dev_priv->mm_lockoverflow%08x : %08x P p X Y dirty purgeable userptr uncached snooped L3+LLC WT LLC %s [%d]: %08x %8u %02x %02x [ %02x ] %02x (name: %d) (fence: %d) yesnounknownno error state collected %s Time: %ld s %ld us Kernel: 3.19.0-80-generic Reset count: %u Suspend count: %u PCI ID: 0x%04x EIR: 0x%08x IER: 0x%08x GTIER gt %d: 0x%08x GTIER: 0x%08x PGTBL_ER: 0x%08x FORCEWAKE: 0x%08x DERRMR: 0x%08x CCID: 0x%08x Missed interrupts: 0x%08lx fence[%d] = %08llx INSTDONE_%d: 0x%08x ERROR: 0x%08x DONE_REG: 0x%08x ERR_INT: 0x%08x %s command stream: START: 0x%08x HEAD: 0x%08x TAIL: 0x%08x CTL: 0x%08x HWS: 0x%08x ACTHD: 0x%08x %08x IPEIR: 0x%08x IPEHR: 0x%08x INSTDONE: 0x%08x BBADDR: 0x%08x %08x BB_STATE: 0x%08x INSTPS: 0x%08x INSTPM: 0x%08x FADDR: 0x%08x %08x RC PSMI: 0x%08x FAULT_REG: 0x%08x GFX_MODE: 0x%08x PDP%d: 0x%016llx PP_DIR_BASE: 0x%08x seqno: 0x%08x waiting: %s ring->head: 0x%08x ring->tail: 0x%08x hangcheck: %s [%d] vm[%d] ActivePinned (submitted by %s [%d]) --- gtt_offset = 0x%08x %s --- %d requests %s --- ringbuffer = 0x%08x %s --- HW Status = 0x%08x [%04x] %08x %08x %08x %08x %s --- HW Context = 0x%08x Semaphore page = 0x%08x resetcontinueGPU HANG: ecode %d:%d:0x%08x, in %s [%d], reason: %s, action: %s6[drm] %s idlewaitactiveactive (loop)kickhungrenderbsdbltveboxbsd2spurious interrupt CRC buffer overflowing longshortdigital hpd port %c - %s L3_PARITY_ERROR=1ROW=%dBANK=%dSUBBANK=%dSLICE=%dERROR=1RESET=1ERROR=0resetting chip Invalid crtc %d crtc %d is disabled Audio CP request interrupt Audio CP change interrupt pipe %c FDI IIR: 0x%08x PCH poison interrupt Poison interrupt PCH HDCP audio interrupt Unexpected DE Misc interrupt Interrupt when HPD disabled Unexpected DE Port interrupt WARN_ON(dev_priv->rps.pm_iir)3i915_bpo: IPEIR: 0x%08x 3i915_bpo: IPEHR: 0x%08x 3i915_bpo: INSTPS: 0x%08x 3i915_bpo: ACTHD: 0x%08x 3i915_bpo: page table error 3i915_bpo: INSTPM: 0x%08x EIR stuck: 0x%08x, masking stuckno progressKicking stuck wait on %sKicking stuck semaphore on %s6[drm] %s on %s Ring hungobjstruct drm_i915_gem_object *devu32freqobj=%p, size=%u , mappablevm=%p (%s), 0x%llx-0x%llx obj=%p, offset=%u, len=%u , writableGTTCPUobj=%p, %s index=%u %s obj=%p dev=%d, size=%d, align=%d %s dev=%d dev=%d, vm=%p dev=%u, ring=%u, seqno=%u yes (NB)noplane=%d, obj=%p writereadnew_freq=%u dev=%u, vm=%p dev=%u, ctx=%p, ctx_vm=%p (null)pipeenum pipeframescanlineminmaxsizevmstruct i915_address_space *offsetu64flagsunsignedstartendname__data_loc char[]pdefirstlastcur_ptesread_domainswrite_domainlenindexgttboolalignsync_fromsync_toseqnoringinvalidateflushblockingplaneintvalregu16ctxstruct intel_context *to%*pbi915Never submitted head request Execlists enabled for %s WARN_ON(to != request->ctx)sol reset is gen7 only WARN_ON_ONCE(w->count == 0)Could not set to CPU domain Could not get object pages Failed to populate LRC: %d ring init context: %d &ring->irq_queuerender ringWARN_ON(ring->id != RCS)bsd ringblitter ringvideo enhancement ringbds2 ringWARN_ON(ring->scratch.obj)WARN_ON(ring->id != RCS)WARN_ON(ring->buffer)&ring->irq_queue%s hws offset: 0x%08x WARN_ON(ringbuf->obj)render ringFailed to allocate batch bo Failed to ping batch bo bsd ringbsd2 ringblitter ringvideo enhancement ringWARN_ON_ONCE(w->count == 0)init render state: %d Device suspended GT wake FIFO error 0x%x readingwriting tobeforeafterWARN_ON(d->wake_count)WARN_ON(d->reg_set == 0)unknownWARN_ON(id)WARN_ON(domain->wake_count)WARN_ON(active_domains)6[drm] Found %zuMB of eLLC renderblittermediaDisable audio codec WARN_ON(port == PORT_A)ELD size %d VBT header incomplete $VBTVBT invalid signature BDB header incomplete BDB incomplete Using VBT from %s: %20s lowhighSDVOBSDVOCSet default to SSC at %d kHz OpRegionPCI ROMcrt_ddc_bus_pin: %d VBT initial LVDS value %x Incorrect SDVO port. Skip it Found MIPI as LFP DRRS State Enabled:%d No PSR BDB found. No MIPI config BDB foundFound MIPI sequence block Found mipi sequence - %d undefined sequence Unknown element Port %c is analog Port %c is TMDS compatible Port %c is internal DP ThinkCentre A57LCPLL1 not enabled Unknown cd freq selection endis%sabling fdi C rx onoffenabling CxSR downclocking disabling CxSR downclocking FDI_RX_IIR 0x%x FDI train 1 done, level %i. FDI train 2 done, level %i. FDI train done. FDI train 1 done. FDI train 2 done. FDI train 1 fail! FDI train 2 fail! enableddisabledCURSORSTANDARDcpu_transcoder: %c pipe bpp: %i, dithering: %i audio: %i, infoframes: %i requested mode: adjusted mode: port clock: %d pipe src size: %dx%d ips: %i double wide: %i planes on this crtc cdclk change in progress buffer is too small cursor cannot be tiled [CRTC:%d] pipe state doesn't match! [hw state][sw state]WARN_ON(num_connectors == 0)WARN_ON_ONCE(!target_freq)WARN_ON_ONCE(1)Incorrect port type Failed to write to D_COMP PLANECRTCLP PCH doesn't have FDI %s pll hw state mismatch pipe_off wait timed out WARN_ON(max_pixclk < 0)WARN_ON(!HAS_PCH_SPLIT(dev))WARN_ON(pll == NULL)WARN_ON(pll->active == 0)WARN_ON(!pll->on)disabling %s WARN_ON(pll->on)enabling %s WARN_ON(HAS_DDI(dev))PLL %d failed to lock DPLL %d failed to lock FDI train done failed to alloc fb WARN_ON(obj == NULL)tiledlinearNo Y tiling for legacy addfb Unsupported tiling 0x%llx! unsupported pixel format: %s framebuffer init failed %d intel fb init failed initial plane fb obj %p WARN_ON(!dst_w || !dst_h)Removing stuck page flip WARN_ON(ret)bad %s crtc mask WARN_ON(pll->active)WARN_ON(!encoder)CRTC:%d allocated %s using %s for pipe %c Unexpected PCH type %d for crtc_state = %p WARN_ON_ONCE(!HAS_DDI(dev))unsupported CDCLK freq %dDisplay already initialized DBuf power enable timeout! DBuf power disable timeout! DBuf power disable timeout Couldn't disable DPLL0 Changing CDCLK to %dKHz DBuf power enable timeout DPLL0 not locked WARN_ON(!HAS_DDI(dev))Encoder config failure CRTC fixup failed [modeset]Unsupported divider value WARN_ON(!crtc->state->enable)setting up %s Using SSC on panel Using SSC on eDP Disabling SSC entirely probing SDVOB probing HDMI on SDVOB probing SDVOC probing HDMI on SDVOC Enabling package C8+ CRTC for pipe %c enabled Power well on SPLL enabled WRPLL1 enabled WRPLL2 enabled Panel power on CPU PWM1 enabled CPU PWM2 enabled PCH PWM1 enabled Utility pin enabled PCH GTC enabled IRQs enabled Switching to FCLK failed LCPLL still locked Disabling package C8+ LCPLL not locked yet downclocking LVDS failed to downclock LVDS! WARN_ON(!in_interrupt())[CONNECTOR:%d:%s] wrong connector dpms state encoder not enabled WARN_ON(!encoder->base.crtc) crtc not enabled crtc not active [ENCODER:%d:%s] active encoder with no crtc [CRTC:%d] [NOFB] failed to attach phys object WARN_ON(!obj)WARN_ON(!encoder->crtc)no such CRTC id [CRTC:%d] found active mode: WARN_ON(crtc->active)[setup_hw_state]s&dev_priv->pps_mutex%d display pipe%s available. PCH DPLL APCH DPLL Bfailed to read control word failed to write control word Num Pipes: %d PWR_WELL_CTL2: %08x Pipe [%d]: Power: %s SRC: %08x STAT: %08x Plane [%d]: CNTR: %08x STRIDE: %08x SIZE: %08x POS: %08x ADDR: %08x SURF: %08x TILEOFF: %08x Cursor [%d]: BASE: %08x CPU transcoder: %c CONF: %08x HTOTAL: %08x HBLANK: %08x HSYNC: %08x VTOTAL: %08x VBLANK: %08x VSYNC: %08x NCR Corporationenabled fbc on plane %c FBC idle timed out disabled FBC disabled per chip default no output, disabling pipe %c underrun CPU pipe %c FIFO underrun upclocking LVDS failed to upclock LVDS! audioBroadcast RGBAutomaticFullLimited 16:235force-dvioffautoonWARN_ON(!obj)WARN_ON(overlay->active)WARN_ON(!overlay->active)overlay underrun, DOVSTA: %x userspace bug: no overlay WARN_ON(dev_priv->overlay) Register file at 0x%08lx: OBUF_0Y: 0x%08x OBUF_1Y: 0x%08x OBUF_0U: 0x%08x OBUF_0V: 0x%08x OBUF_1U: 0x%08x OBUF_1V: 0x%08x OSTRIDE: 0x%08x YRGB_VPH: 0x%08x UV_VPH: 0x%08x HORZ_PH: 0x%08x INIT_PHS: 0x%08x DWINPOS: 0x%08x DWINSZ: 0x%08x SWIDTH: 0x%08x SWIDTHSW: 0x%08x SHEIGHT: 0x%08x YRGBSCALE: 0x%08x UVSCALE: 0x%08x OCLRC0: 0x%08x OCLRC1: 0x%08x DCLRKV: 0x%08x DCLRKM: 0x%08x SCLRKVH: 0x%08x SCLRKVL: 0x%08x SCLRKEN: 0x%08x OCONFIG: 0x%08x OCMD: 0x%08x OSTART_0Y: 0x%08x OSTART_1Y: 0x%08x OSTART_0U: 0x%08x OSTART_0V: 0x%08x OSTART_1U: 0x%08x OSTART_1V: 0x%08x OTILEOFF_0Y: 0x%08x OTILEOFF_1Y: 0x%08x OTILEOFF_0U: 0x%08x OTILEOFF_0V: 0x%08x OTILEOFF_1U: 0x%08x OTILEOFF_1V: 0x%08x FASTHSCALE: 0x%08x UVSCALEV: 0x%08x WARN_ON(dev_priv->psr.active)PSR already in use HSW ties PSR to DDI A (eDP) PSR disable by flag &dev_priv->psr.lockreadwriteWrong plane <-> crtc mapping WARN_ON(!can_scale)bad typefailed to evaluate _DSM MUX info connectors: %lld Connector id: 0x%016llx port id: %s display mux info: %s aux/dc mux info: %s hpd mux info: %s unknownNo MUX, iGPU onlyNo MUX, dGPU onlyMUXed between iGPU and dGPUReservedAnalog VGALVDSHDMI/DVI_BHDMI/DVI_CHDMI/DVI_DDisplayPort_ADisplayPort_BDisplayPort_CDisplayPort_DWiDiSWSCI request timed out SWSCI request error %u Illum is not supported bclp = 0x%08x Pfit is not supported PWM freq is not supported SROT is not supported ISCT is not supported video_ADRACPI OpRegion not supported! IntelGraphicsMemopregion signature mismatch SWSCI supported ASLE supported i915_bpoiWARN_ON(!encoder->crtc)Enabled: %i, detected: %i failed to pin obj: %d WARN_ON(!intel_fb->obj)re-using BIOS fb pipe %c not active, skipping failed to restore crtc mode CH7017_LVDS_CONTROL_2: %02x CH7017_OUTPUTS_ENABLE: %02x CH7017_LVDS_POWER_DOWN: %02x Registers after mode setting ch7017ch7018ch7019%s detected on %s, addr %d %02X: %02X CH7XXXCH7010BCH7011CH7009ACH7009BCH7301VR00: 0x%04x VR01: 0x%04x VR10: 0x%04x VR30: 0x%04x VR40: 0x%04x VR80: 0x%04x VR81: 0x%04x VR82: 0x%04x VR83: 0x%04x VR84: 0x%04x VR85: 0x%04x VR86: 0x%04x VR87: 0x%04x VR88: 0x%04x VR8E: 0x%04x VR8F: 0x%04x SIL164_FREQ_LO: 0x%02x SIL164_FREQ_HI: 0x%02x SIL164_REG8: 0x%02x SIL164_REG9: 0x%02x SIL164_REGC: 0x%02x TFP410_REV: 0x%02X TFP410_CTL1: 0x%02X TFP410_CTL2: 0x%02X TFP410_CTL3: 0x%02X TFP410_USERCFG: 0x%02X TFP410_DE_DLY: 0x%02X TFP410_DE_CTL: 0x%02X TFP410_DE_TOP: 0x%02X TFP410_DE_CNT: 0x%02X%02X TFP410_DE_LIN: 0x%02X%02X TFP410_H_RES: 0x%02X%02X TFP410_V_RES: 0x%02X%02X WARN_ON(!intel_crtc->config)CRTCPLANEWARN_ON(*scaler_id < 0)Cannot find scaler for %s:%d WARN_ON(!plane->state)Unknown plane property '%s' crt adpa set to 0x%x Disabling SPLL SPLL already enabled [CONNECTOR:%d:%s] force=%d CRT detected via hotplug CRT not detected via hotplug starting load-detect on CRT ACER ZGBDELL XPS 8700Invalid DDI encoder type %d PLL %d not locked bad wrpll refclk DPLL %d not locked timeout waiting for PHY1 GRC FDI link training failed! bad spll freq bad port clock sel Unsupported link rate Incorrect PDiv Incorrect KDiv WARN_ON(best_clock.m1 != 2)Invalid VCO Unknown link rate WARN_ON(dpll != SKL_DPLL0)DPLL 1DPLL 2DPLL 3PORT PLL APORT PLL BPORT PLL CWRPLL 1WRPLL 2CDCLK running at %dKHz LCPLL1 is disabled CDCLK source is not LCPLL LCPLL is disabled WARN_ON(HAS_DDI(dev)) DRRS not supported. Unsupported refreshrate type [CONNECTOR:%d:%s] no scaling not supported dp pll off, should be on eDP PLL enable for clock %d dp pll on, should be off Turning eDP port %c VDD off WARN_ON(!is_edp(intel_dp))WARN_ON(pipes == 0)Sink OUI: %02hx%02hx%02hx Branch OUI: %02hx%02hx%02hx Sink is MST capable Sink is not MST capable eDP port %c VDD not forced on, %s%dsource rates: %s sink rates: %s common rates: %s supportednot supportedDPCD: %*ph Detected EDP PSR Panel. PSR2 %s on sinkDisplayport TPS3 supported LINK_TRAINING test requested TEST_PATTERN test requested EDID test requested PHY_PATTERN test requested Invalid test request '%02x' Wait complete Wait for panel power cycle Turning eDP port %c VDD on Status 0x%08x Control 0x%08x WARN_ON(txsize > 20)WARN_ON(rxsize > 20)Wait for panel power on Using signal levels %08x Using vswing level %d Using pre-emphasis level %d enabledisableWARN_ON(!IS_VALLEYVIEW(dev))WARN_ON(common_len <= 0)WARN_ON(len <= 0)failed to get link status clock recovery OK clock recovery not ok, resetfailed to train DP, aborting got esi %3ph got esi2 %3ph longshortgot hpd irq on port %c - %s WARN_ON(dp_reg & DP_PORT_EN)Enabling DP audio on pipe %c Panel doesn't support DRRS WARN_ON(dev_priv->drrs.dp)DRRS already enabled eDPDPDPDDC-ADPDDC-BDPDDC-CDPDDC-DDPDDC-Eregistering %s bus for %s &dev_priv->drrs.mutexVBT doesn't support DRRS %d can't find connector failed to allocate vcpi failed to update payload %d pipe %c MODE_NO_DBLESCAN no fixed mode drm_mode_duplicate failed DPI FIFOs are not empty DSI LP not going Low no device found DSI CLK Out of Range dsi_calc_mnp failed dsi pll div %08x, ctrl %08x DSI PLL locked DSI PLL lock failed wrong P1 divisor wrong m_seed programmed Starting MIPI sequence - %s no dsi device for port %c enableddisabledcommandvideo Burst mode target is not set Eot %s Clockstop %s Mode %s Dual link: NONE Pixel Format %d TLPX %d LP RX Timeout 0x%x Turnaround Timeout 0x%x Init Count 0x%x HS to LP Count 0x%x LP Byte Clock %d DBI BW Timer 0x%x LP to HS Clock Count 0x%x HS to LP Clock Count 0x%x BTA %s UNDEFINEDMIPI_SEQ_ASSERT_RESETMIPI_SEQ_INIT_OTPMIPI_SEQ_DISPLAY_ONMIPI_SEQ_DISPLAY_OFFMIPI_SEQ_DEASSERT_RESET[CONNECTOR:%d:%s] sil164ch7xxxivchtfp410ch7017ns2501couldn't fill AVI infoframe Integrated gfxIntelcouldn't fill SPD infoframe [CONNECTOR:%d:%s] Live status not up!unknown info frame type %d WARN_ON(IS_BROXTON(dev_priv))&dev_priv->gmbus_mutex&dev_priv->gmbus_wait_queuei915 gmbus %sendisdpbdpcmiscdpdvgasscpanelCan't support LVDS on pipe A [CONNECTOR:%d:%s] no scaling not supported dualsingleLVDS is not present in VBT disable LVDS for eDP support using mode from VBT: using current (BIOS) mode: Apple MacBook Pro 15" (2010)Apple MacBook Pro 15" (2011)Apple MacBook Pro 15" (2012)Apple Mac Mini (Core series)MSI IM-945GSE-ADell Studio HybridDell OptiPlex FX170AOpen Mini PCAOpen Mini PC MP915AOpen i915GMm-HFSAOpen i45GMx-IAopen i945GTt-VFAClientron U800Clientron E830Asus EeeBox PC EB1007Asus AT5NM10T-IHewlett-Packard HP t5740Hewlett-Packard t5745Hewlett-Packard st5747MSI Wind Box DC500Gigabyte GA-D525TUDSupermicro X7SPA-HFujitsu Esprimo Q900Intel D410PTIntel D425KTIntel D510MOIntel D525MWToshiba Tecra A11set backlight PWM = %d backlight already enabled get backlight PWM = %d bad panel fit mode: %d pipe %c enableddisabledno backlight present per VBT intel_backlighti2c transfer returned %d SDVOBSDVOC(%s)(??? %d) %02X%s: R: %s %s: R: ... failed %02X %s: W: %02X %s (%02X)I2c transfer returned %d I2c transfer returned %d/%d left_marginright_margintop_marginbottom_marginhposvpossaturationcontrasthuesharpnessbrightnessflicker_filterflicker_filter_adaptiveflicker_filter_2dtv_chroma_filtertv_luma_filterdot_crawldot crawl: current %d No enhancement is supported failed to retrieve SDVO DTD forcing bpc to 8 for SDVO couldn't fill AVI infoframe [CONNECTOR:%d:%s] SDVO response %d %d [%x] initialising DVI device %d initialising TV type %d modeinitialising LVDS device %d No SDVO device found on %s Power onSuccessNot supportedInvalid argPendingTarget not specifiedScaling not supportedSDVO_CMD_RESETSDVO_CMD_GET_DEVICE_CAPSSDVO_CMD_GET_FIRMWARE_REVSDVO_CMD_GET_TRAINED_INPUTSSDVO_CMD_GET_ACTIVE_OUTPUTSSDVO_CMD_SET_ACTIVE_OUTPUTSSDVO_CMD_GET_IN_OUT_MAPSDVO_CMD_SET_IN_OUT_MAPSDVO_CMD_GET_HOT_PLUG_SUPPORTSDVO_CMD_SET_ACTIVE_HOT_PLUGSDVO_CMD_GET_ACTIVE_HOT_PLUGSDVO_CMD_SET_TARGET_INPUTSDVO_CMD_SET_TARGET_OUTPUTSDVO_CMD_GET_CLOCK_RATE_MULTSDVO_CMD_SET_CLOCK_RATE_MULTSDVO_CMD_GET_TV_FORMATSDVO_CMD_SET_TV_FORMATSDVO_CMD_GET_POWER_STATESDVO_CMD_GET_MAX_HPOSSDVO_CMD_GET_HPOSSDVO_CMD_SET_HPOSSDVO_CMD_GET_MAX_VPOSSDVO_CMD_GET_VPOSSDVO_CMD_SET_VPOSSDVO_CMD_GET_MAX_SATURATIONSDVO_CMD_GET_SATURATIONSDVO_CMD_SET_SATURATIONSDVO_CMD_GET_MAX_HUESDVO_CMD_GET_HUESDVO_CMD_SET_HUESDVO_CMD_GET_MAX_CONTRASTSDVO_CMD_GET_CONTRASTSDVO_CMD_SET_CONTRASTSDVO_CMD_GET_MAX_BRIGHTNESSSDVO_CMD_GET_BRIGHTNESSSDVO_CMD_SET_BRIGHTNESSSDVO_CMD_GET_MAX_OVERSCAN_HSDVO_CMD_GET_OVERSCAN_HSDVO_CMD_SET_OVERSCAN_HSDVO_CMD_GET_MAX_OVERSCAN_VSDVO_CMD_GET_OVERSCAN_VSDVO_CMD_SET_OVERSCAN_VSDVO_CMD_GET_FLICKER_FILTERSDVO_CMD_SET_FLICKER_FILTERSDVO_CMD_GET_MAX_SHARPNESSSDVO_CMD_GET_SHARPNESSSDVO_CMD_SET_SHARPNESSSDVO_CMD_GET_DOT_CRAWLSDVO_CMD_SET_DOT_CRAWLSDVO_CMD_GET_TV_CHROMA_FILTERSDVO_CMD_SET_TV_CHROMA_FILTERSDVO_CMD_GET_TV_LUMA_FILTERSDVO_CMD_SET_TV_LUMA_FILTERSDVO_CMD_GET_SUPP_ENCODESDVO_CMD_GET_ENCODESDVO_CMD_SET_ENCODESDVO_CMD_SET_PIXEL_REPLISDVO_CMD_GET_PIXEL_REPLISDVO_CMD_GET_COLORIMETRY_CAPSDVO_CMD_SET_COLORIMETRYSDVO_CMD_GET_COLORIMETRYSDVO_CMD_SET_AUDIO_STATSDVO_CMD_GET_AUDIO_STATSDVO_CMD_GET_HBUF_INDEXSDVO_CMD_SET_HBUF_INDEXSDVO_CMD_GET_HBUF_INFOSDVO_CMD_GET_HBUF_AV_SPLITSDVO_CMD_SET_HBUF_AV_SPLITSDVO_CMD_GET_HBUF_TXRATESDVO_CMD_SET_HBUF_TXRATESDVO_CMD_SET_HBUF_DATASDVO_CMD_GET_HBUF_DATANTSC_MNTSC_JNTSC_443PAL_BPAL_DPAL_GPAL_HPAL_IPAL_MPAL_NPAL_NCPAL_60SECAM_BSECAM_DSECAM_GSECAM_KSECAM_K1SECAM_LSECAM_60forcing bpc to 8 for TV [CONNECTOR:%d:%s] force=%d TV detected: %x, %x Unrecognised TV connection NTSC-M640x480800x6001024x7681280x1024848x4801280x7201920x1080NTSC-443NTSC-JPAL-MPAL-NPAL480p576p720p@60Hz720p@50Hz1080i@50Hz1080i@60HzVGT deballoon. VGT balloon fail unknown parameter %d 6i915_bpo: switched on 3i915_bpo: switched off Unknown parameter %d copy_to_user failed ynslice total: %u subslice total: %u subslice per slice: %u EU total: %u EU per subslice: %u has slice power gating: %s has EU power gating: %s has_fpga_dbg,has_ddi,has_llc,supports_tv,overlay_needs_physical,has_overlay,cursor_needs_physical,has_hotplug,has_pipe_cxsr,has_fbc,is_preliminary,is_skylake,is_haswell,is_valleyview,is_ivybridge,is_crestline,is_broadwater,is_pineview,is_g4x,need_gfx_hws,is_g33,is_i945gm,is_i915g,is_i85x,is_mobile,&dev_priv->backlight_lock&dev_priv->sb_lock&dev_priv->csr_lockbridge device not found failed to map registers inteldrmfbi915i915-dpi915-hangchecki915 MCHBARfailed bus alloc: %d failed to init modeset failed to idle hardware: %d I915_INITI915_FLUSHI915_FLIPI915_BATCHBUFFERI915_IRQ_EMITI915_IRQ_WAITI915_GETPARAMI915_SETPARAMI915_ALLOCI915_FREEI915_INIT_HEAPI915_CMDBUFFERI915_DESTROY_HEAPI915_SET_VBLANK_PIPEI915_GET_VBLANK_PIPEI915_VBLANK_SWAPI915_HWS_ADDRI915_GEM_INITI915_GEM_EXECBUFFERI915_GEM_PINI915_GEM_UNPINI915_GEM_BUSYI915_GEM_THROTTLEI915_GEM_ENTERVTI915_GEM_LEAVEVTI915_GEM_CREATEI915_GEM_PREADI915_GEM_PWRITEI915_GEM_MMAPI915_GEM_SET_DOMAINI915_GEM_SW_FINISHI915_GEM_SET_TILINGI915_GEM_GET_TILINGI915_GEM_GET_APERTUREI915_GEM_MMAP_GTTI915_GET_PIPE_FROM_CRTC_IDI915_GEM_MADVISEI915_OVERLAY_PUT_IMAGEI915_OVERLAY_ATTRSI915_GEM_EXECBUFFER2I915_GET_SPRITE_COLORKEYI915_SET_SPRITE_COLORKEYI915_GEM_WAITI915_GEM_CONTEXT_CREATEI915_GEM_CONTEXT_DESTROYI915_GEM_SET_CACHINGI915_GEM_GET_CACHINGI915_REG_READI915_GET_RESET_STATSI915_GEM_USERPTRI915_GEM_CONTEXT_GETPARAMI915_GEM_CONTEXT_SETPARAMlicense=GPL and additional rightsdescription=Intel Graphicsauthor=Intel Corporationauthor=Tungsten Graphics, Inc.parm=edp_vswing:Ignore/Override vswing pre-emph table selection from VBT (0=use value from vbt [default], 1=low power swing(200mV),2=default swing(400mV))parmtype=edp_vswing:intparm=nuclear_pageflip:Force atomic modeset functionality; only planes work for now (default: false).parmtype=nuclear_pageflip:boolparm=verbose_state_checks:Enable verbose logs (ie. WARN_ON()) in case of unexpected hw state conditions.parmtype=verbose_state_checks:boolparm=mmio_debug:Enable the MMIO debug code for the first N failures (default: off). This may negatively affect performance.parmtype=mmio_debug:intparm=use_mmio_flip:use MMIO flips (-1=never, 0=driver discretion [default], 1=always)parmtype=use_mmio_flip:intparm=enable_cmd_parser:Enable command parsing (1=enabled [default], 0=disabled)parmtype=enable_cmd_parser:intparm=disable_vtd_wa:Disable all VT-d workarounds (default: false)parmtype=disable_vtd_wa:boolparm=disable_display:Disable display (default: false)parmtype=disable_display:boolparm=invert_brightness:Invert backlight brightness (-1 force normal, 0 machine defaults, 1 force inversion), please report PCI device ID, subsystem vendor and subsystem device ID to dri-devel@lists.freedesktop.org, if your machine needs it. It will then be included in an upcoming module version.parmtype=invert_brightness:intparm=load_detect_test:Force-enable the VGA load detect code for testing (default:false). For developers only.parmtype=load_detect_test:boolparm=prefault_disable:Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.parmtype=prefault_disable:boolparm=fastboot:Try to skip unnecessary mode sets at boot time (default: false)parmtype=fastboot:boolparm=enable_ips:Enable IPS (default: true)parmtype=enable_ips:intparm=disable_power_well:Disable display power wells when possible (-1=auto [default], 0=power wells always on, 1=power wells disabled when possible)parmtype=disable_power_well:intparm=preliminary_hw_support:Enable preliminary hardware support.parmtype=preliminary_hw_support:intparm=enable_psr:Enable PSR (default: false)parmtype=enable_psr:intparm=enable_execlists:Override execlists usage. (-1=auto [default], 0=disabled, 1=enabled)parmtype=enable_execlists:intparm=enable_ppgtt:Override PPGTT usage. (-1=auto [default], 0=disabled, 1=aliasing, 2=full)parmtype=enable_ppgtt:intparm=enable_hangcheck:Periodically check GPU activity for detecting hangs. WARNING: Disabling this can cause system wide hangs. (default: true)parmtype=enable_hangcheck:boolparm=reset:Attempt GPU resets (default: true)parmtype=reset:boolparm=vbt_sdvo_panel_type:Override/Ignore selection of SDVO panel mode in the VBT (-2=ignore, -1=auto [default], index in VBT BIOS table)parmtype=vbt_sdvo_panel_type:intparm=lvds_use_ssc:Use Spread Spectrum Clock with panels [LVDS/eDP] (default: auto from VBT)parmtype=lvds_use_ssc:intparm=lvds_channel_mode:Specify LVDS channel mode (0=probe BIOS [default], 1=single-channel, 2=dual-channel)parmtype=lvds_channel_mode:intparm=lvds_downclock:Use panel (LVDS/eDP) downclocking for power savings (default: false)parmtype=lvds_downclock:intparm=enable_fbc:Enable frame buffer compression for power savings (default: -1 (use per-chip default))parmtype=enable_fbc:intparm=enable_rc6:Enable power-saving render C-state 6. Different stages can be selected via bitmask values (0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. default: -1 (use per-chip default)parmtype=enable_rc6:intparm=semaphores:Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))parmtype=semaphores:intparm=panel_ignore_lid:Override lid status (0=autodetect, 1=autodetect disabled [default], -1=force lid closed, -2=force lid open)parmtype=panel_ignore_lid:intparm=modeset:Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, 1=on, -1=force vga console preference [default])parmtype=modeset:intfirmware=i915/skl_dmc_ver1.binsrcversion=244EBA3D7AB2A5509B79C3Calias=pci:v00008086d0000192Asv*sd*bc03sc*i*alias=pci:v00008086d0000192Bsv*sd*bc03sc*i*alias=pci:v00008086d00001926sv*sd*bc03sc*i*alias=pci:v00008086d0000191Dsv*sd*bc03sc*i*alias=pci:v00008086d0000191Asv*sd*bc03sc*i*alias=pci:v00008086d0000191Bsv*sd*bc03sc*i*alias=pci:v00008086d00001912sv*sd*bc03sc*i*alias=pci:v00008086d0000191Esv*sd*bc03sc*i*alias=pci:v00008086d00001921sv*sd*bc03sc*i*alias=pci:v00008086d00001916sv*sd*bc03sc*i*alias=pci:v00008086d0000190Asv*sd*bc03sc*i*alias=pci:v00008086d0000190Bsv*sd*bc03sc*i*alias=pci:v00008086d00001902sv*sd*bc03sc*i*alias=pci:v00008086d0000190Esv*sd*bc03sc*i*alias=pci:v00008086d00001906sv*sd*bc03sc*i*alias=pci:v00008086d000022B3sv*sd*bc03sc*i*alias=pci:v00008086d000022B2sv*sd*bc03sc*i*alias=pci:v00008086d000022B1sv*sd*bc03sc*i*alias=pci:v00008086d000022B0sv*sd*bc03sc*i*alias=pci:v00008086d0000162Dsv*sd*bc03sc*i*alias=pci:v00008086d0000162Asv*sd*bc03sc*i*alias=pci:v00008086d0000162Esv*sd*bc03sc*i*alias=pci:v00008086d0000162Bsv*sd*bc03sc*i*alias=pci:v00008086d00001626sv*sd*bc03sc*i*alias=pci:v00008086d00001622sv*sd*bc03sc*i*alias=pci:v00008086d0000161Dsv*sd*bc03sc*i*alias=pci:v00008086d0000161Asv*sd*bc03sc*i*alias=pci:v00008086d0000160Dsv*sd*bc03sc*i*alias=pci:v00008086d0000160Asv*sd*bc03sc*i*alias=pci:v00008086d0000161Esv*sd*bc03sc*i*alias=pci:v00008086d0000161Bsv*sd*bc03sc*i*alias=pci:v00008086d00001616sv*sd*bc03sc*i*alias=pci:v00008086d00001612sv*sd*bc03sc*i*alias=pci:v00008086d0000160Esv*sd*bc03sc*i*alias=pci:v00008086d0000160Bsv*sd*bc03sc*i*alias=pci:v00008086d00001606sv*sd*bc03sc*i*alias=pci:v00008086d00001602sv*sd*bc03sc*i*depends=drm_kms_helper,drm,video,intel_ips,i2c-algo-bitintree=Yvermagic=3.19.0-80-generic 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se_mmap.part.45i915_gem_object_retire__writei915_gem_request_retire__i915_gem_request_retire__uptoi915_gem_object_finish_gtti915_gem_object_retire__readi915_gem_object_retire_requesti915_gem_object_get_pages_gtt__func__.56875__func__.56937i915_gem_object_wait_fencei915_gem_object_wait_rendering__nonblockingi915_gem_object_flush_active.part.50i915_gem_init_seqnoi915_gem_retire_work_handleri915_gem_object_flush_cpu_write_domain.part.54i915_gem_object_put_pages_physi915_gem_object_put_pages_gtti915_gem_object_opsi915_gem_create__warned.57803__func__.58116__func__.58203i915_gem_write_fencei915_gem_object_update_fencei915_gem_phys_opsi915_gem_object_do_pin__func__.57414__warned.57653__func__.57449__warned.56797__key.58147__key.58184__key.58185.LC8.LC14i915_gem_shrinker_locki915_gem_shrinker_count__warned.24771i915_gem_shrinker_scani915_gem_shrinker_oomi915_gem_object_release_stoleni915_gem_object_get_pages_stoleni915_gem_object_put_pages_stoleni915_gem_object_pin_pages.isra.1.part.2_i915_gem_object_create_stoleni915_gem_object_stolen_ops__func__.54504__print_once.54454__func__.54453__func__.54481__func__.54408__func__.54535__func__.54548__i915_mm_struct_free__worker__i915_mm_struct_freei915_gem_userptr_put_pageskref_get.part.6__i915_gem_userptr_set_pagesi915_gem_userptr_releasei915_gem_userptr_init__mmu_notifieri915_gem_userptr_notifieri915_gem_userptr_dmabuf_exporti915_gem_userptr_get_pages__i915_gem_userptr_get_pages_workercancel_userptri915_gem_userptr_mn_invalidate_range_starti915_gem_userptr_ops__key.57351__i915_error_ok__i915_error_advancei915_error_vprintfi915_error_object_freei915_error_state_freei915_error_putscapture_bo.isra.7i915_error_object_createi915_record_ring_stateCSWTCH.226print_error_objprint_error_buffersCSWTCH.189CSWTCH.196__warned.9681__func__.55122warned.55118i8xx_get_vblank_counteri915_get_vblank_countergm45_get_vblank_counter__intel_get_crtc_scanlineibx_irq_resetgen5_gt_irq_resetironlake_irq_resetvlv_display_irq_resetvalleyview_irq_preinstallgen8_gt_irq_resetcherryview_irq_preinstallironlake_irq_uninstalli8xx_irq_preinstalli8xx_irq_uninstalli915_irq_preinstalli915_irq_uninstalli965_irq_preinstalli965_irq_uninstalli915_hpd_irq_setuphpd_mask_i915ilk_update_gt_irqsnb_update_pm_irqibx_irq_pre_postinstallgen5_gt_irq_postinstallibx_irq_postinstallbxt_hpd_irq_setuphpd_bxt__warned.55997gen8_gt_irq_postinstallgen8_disable_vblankgen8_enable_vblankvlv_c0_readdisplay_pipe_crc_irq_handler__func__.55126i9xx_pipe_crc_irq_handlerhsw_pipe_crc_irq_handlerintel_hpd_irq_handler__warned.55072__func__.55071CSWTCH.185valleyview_pipestat_irq_handlerCSWTCH.258gen8_irq_postinstallgen8_irq_resetgen8_irq_uninstalli915_get_crtc_scanoutpos__func__.54684semaphore_passedivybridge_parity_work__warned.54913__func__.54943vlv_get_pipestat_enable_mask.isra.7__warned.54570__warned.54565i915_error_wake_upi915_reset_and_wakeup__func__.55540notify_ringi8xx_irq_handler__func__.56315snb_gt_irq_handler__func__.54993i9xx_get_hpd_pins.part.11__func__.55056i9xx_hpd_irq_handlerhpd_status_g4xhpd_status_i915pch_get_hpd_pins__func__.55045i915_handle_vblanki965_irq_handler__func__.56533i915_irq_handler__func__.56413i915_get_vblank_timestamp__func__.54747cpt_irq_handlerhpd_cpthpd_spt__func__.55330intel_hpd_irq_reenable_work__func__.56596i915_digport_work_funci915_hotplug_work_func__func__.54790__func__.54757ironlake_enable_vblankironlake_irq_postinstallironlake_disable_vblankgen6_pm_rps_workgen6_rps_irq_handler__func__.55178ironlake_irq_handlerhpd_ibx__func__.55271gen8_gt_irq_handlergen8_irq_handler__func__.55441cherryview_irq_handlervalleyview_irq_handleribx_hpd_irq_setup__warned.54540valleyview_display_irqs_installvlv_display_irq_postinstallvalleyview_irq_postinstallcherryview_irq_postinstalli915_enable_vblanki915_enable_asle_pipestati965_irq_postinstalli915_irq_postinstalli8xx_irq_postinstallvalleyview_enable_vblank__warned.54555valleyview_display_irqs_uninstallvlv_display_irq_uninstallvalleyview_irq_uninstallcherryview_irq_uninstalli915_disable_vblankvalleyview_disable_vblanki915_hangcheck_elapsedftrace_define_fields_i915_gem_objectftrace_define_fields_i915_gem_evict_everythingftrace_define_fields_intel_gpu_freq_changeftrace_raw_output_i915_pipe_update_startftrace_raw_output_i915_pipe_update_vblank_evadedftrace_raw_output_i915_pipe_update_endftrace_raw_output_i915_gem_object_createftrace_raw_output_i915_vma_bindftrace_raw_output_i915_vma_unbindftrace_raw_output_i915_vaftrace_raw_output_i915_page_table_entryftrace_raw_output_i915_page_table_entry_updateftrace_raw_output_i915_gem_object_change_domainftrace_raw_output_i915_gem_object_pwriteftrace_raw_output_i915_gem_object_preadftrace_raw_output_i915_gem_object_faultftrace_raw_output_i915_gem_objectftrace_raw_output_i915_gem_evictftrace_raw_output_i915_gem_evict_everythingftrace_raw_output_i915_gem_evict_vmftrace_raw_output_i915_gem_ring_sync_toftrace_raw_output_i915_gem_ring_dispatchftrace_raw_output_i915_gem_ring_flushftrace_raw_output_i915_gem_requestftrace_raw_output_i915_gem_request_notifyftrace_raw_output_i915_gem_request_wait_beginftrace_raw_output_i915_flip_requestftrace_raw_output_i915_flip_completeftrace_raw_output_i915_reg_rwftrace_raw_output_intel_gpu_freq_changeftrace_raw_output_i915_ppgttftrace_raw_output_i915_contextftrace_raw_output_switch_mmperf_trace_i915_vaftrace_raw_event_i915_vaftrace_define_fields_i915_pipe_update_startftrace_define_fields_i915_pipe_update_vblank_evadedftrace_define_fields_i915_pipe_update_endftrace_define_fields_i915_gem_object_createftrace_define_fields_i915_vma_bindftrace_define_fields_i915_vma_unbindftrace_define_fields_i915_vaftrace_define_fields_i915_page_table_entryftrace_define_fields_i915_page_table_entry_updateftrace_define_fields_i915_gem_object_change_domainftrace_define_fields_i915_gem_object_pwriteftrace_define_fields_i915_gem_object_preadftrace_define_fields_i915_gem_object_faultftrace_define_fields_i915_gem_evictftrace_define_fields_i915_gem_evict_vmftrace_define_fields_i915_gem_ring_sync_toftrace_define_fields_i915_gem_ring_dispatchftrace_define_fields_i915_gem_ring_flushftrace_define_fields_i915_gem_requestftrace_define_fields_i915_gem_request_notifyftrace_define_fields_i915_gem_request_wait_beginftrace_define_fields_i915_flip_requestftrace_define_fields_i915_flip_completeftrace_define_fields_i915_reg_rwftrace_define_fields_i915_ppgttftrace_define_fields_i915_contextftrace_define_fields_switch_mmftrace_raw_event_i915_gem_object_createftrace_raw_event_i915_gem_object_pwriteftrace_raw_event_i915_gem_object_preadftrace_raw_event_i915_gem_object_faultftrace_raw_event_i915_gem_objectftrace_raw_event_i915_gem_evict_everythingftrace_raw_event_i915_gem_evict_vmftrace_raw_event_i915_flip_requestftrace_raw_event_i915_flip_completeftrace_raw_event_i915_reg_rwftrace_raw_event_intel_gpu_freq_changeftrace_raw_event_i915_ppgttftrace_raw_event_i915_gem_object_change_domainftrace_raw_event_i915_gem_evictftrace_raw_event_i915_gem_ring_flushftrace_raw_event_i915_vma_bindftrace_raw_event_i915_vma_unbindftrace_raw_event_i915_page_table_entryftrace_raw_event_i915_pipe_update_endftrace_raw_event_i915_contextftrace_raw_event_switch_mmftrace_raw_event_i915_pipe_update_vblank_evadedftrace_raw_event_i915_gem_ring_sync_toftrace_raw_event_i915_gem_requestftrace_raw_event_i915_gem_request_notifyftrace_raw_event_i915_gem_request_wait_beginftrace_raw_event_i915_gem_ring_dispatchftrace_raw_event_i915_pipe_update_startperf_trace_i915_gem_objectperf_trace_intel_gpu_freq_changeperf_trace_i915_flip_completeperf_trace_i915_flip_requestperf_trace_i915_gem_object_preadperf_trace_i915_gem_evict_everythingperf_trace_i915_gem_object_createperf_trace_i915_gem_object_pwriteperf_trace_i915_ppgttperf_trace_i915_reg_rwperf_trace_i915_gem_object_faultperf_trace_i915_gem_evictperf_trace_i915_gem_evict_vmperf_trace_i915_gem_ring_flushperf_trace_i915_vma_unbindperf_trace_i915_page_table_entryperf_trace_i915_gem_object_change_domainperf_trace_i915_vma_bindperf_trace_i915_pipe_update_vblank_evadedperf_trace_i915_pipe_update_endperf_trace_i915_contextftrace_raw_event_i915_page_table_entry_updateperf_trace_i915_gem_ring_sync_toperf_trace_switch_mmperf_trace_i915_gem_requestperf_trace_i915_gem_request_notifyperf_trace_i915_gem_request_wait_beginperf_trace_i915_gem_ring_dispatchperf_trace_i915_pipe_update_startperf_trace_i915_page_table_entry_update__event_switch_mmevent_switch_mmprint_fmt_switch_mm__event_i915_context_freeevent_i915_context_free__event_i915_context_createevent_i915_context_createprint_fmt_i915_context__event_i915_ppgtt_releaseevent_i915_ppgtt_release__event_i915_ppgtt_createevent_i915_ppgtt_createprint_fmt_i915_ppgtt__event_intel_gpu_freq_changeevent_intel_gpu_freq_changeprint_fmt_intel_gpu_freq_change__event_i915_reg_rwevent_i915_reg_rwprint_fmt_i915_reg_rw__event_i915_flip_completeevent_i915_flip_completeprint_fmt_i915_flip_complete__event_i915_flip_requestevent_i915_flip_requestprint_fmt_i915_flip_request__event_i915_gem_request_wait_endevent_i915_gem_request_wait_end__event_i915_gem_request_wait_beginevent_i915_gem_request_wait_beginprint_fmt_i915_gem_request_wait_begin__event_i915_gem_request_completeevent_i915_gem_request_complete__event_i915_gem_request_retireevent_i915_gem_request_retire__event_i915_gem_request_notifyevent_i915_gem_request_notifyprint_fmt_i915_gem_request_notify__event_i915_gem_request_addevent_i915_gem_request_addprint_fmt_i915_gem_request__event_i915_gem_ring_flushevent_i915_gem_ring_flushprint_fmt_i915_gem_ring_flush__event_i915_gem_ring_dispatchevent_i915_gem_ring_dispatchprint_fmt_i915_gem_ring_dispatch__event_i915_gem_ring_sync_toevent_i915_gem_ring_sync_toprint_fmt_i915_gem_ring_sync_to__event_i915_gem_evict_vmevent_i915_gem_evict_vmprint_fmt_i915_gem_evict_vm__event_i915_gem_evict_everythingevent_i915_gem_evict_everythingprint_fmt_i915_gem_evict_everything__event_i915_gem_evictevent_i915_gem_evictprint_fmt_i915_gem_evict__event_i915_gem_object_destroyevent_i915_gem_object_destroy__event_i915_gem_object_clflushevent_i915_gem_object_clflushprint_fmt_i915_gem_object__event_i915_gem_object_faultevent_i915_gem_object_faultprint_fmt_i915_gem_object_fault__event_i915_gem_object_preadevent_i915_gem_object_preadprint_fmt_i915_gem_object_pread__event_i915_gem_object_pwriteevent_i915_gem_object_pwriteprint_fmt_i915_gem_object_pwrite__event_i915_gem_object_change_domainevent_i915_gem_object_change_domainprint_fmt_i915_gem_object_change_domain__event_i915_page_table_entry_mapevent_i915_page_table_entry_mapprint_fmt_i915_page_table_entry_update__event_i915_page_table_entry_allocevent_i915_page_table_entry_allocprint_fmt_i915_page_table_entry__event_i915_va_allocevent_i915_va_allocprint_fmt_i915_va__event_i915_vma_unbindevent_i915_vma_unbindprint_fmt_i915_vma_unbind__event_i915_vma_bindevent_i915_vma_bindprint_fmt_i915_vma_bind__event_i915_gem_object_createevent_i915_gem_object_createprint_fmt_i915_gem_object_create__event_i915_pipe_update_endevent_i915_pipe_update_endprint_fmt_i915_pipe_update_end__event_i915_pipe_update_vblank_evadedevent_i915_pipe_update_vblank_evadedprint_fmt_i915_pipe_update_vblank_evaded__event_i915_pipe_update_startevent_i915_pipe_update_startprint_fmt_i915_pipe_update_startftrace_event_type_funcs_switch_mmftrace_event_type_funcs_i915_contextftrace_event_type_funcs_i915_ppgttftrace_event_type_funcs_intel_gpu_freq_changeftrace_event_type_funcs_i915_reg_rwftrace_event_type_funcs_i915_flip_completeftrace_event_type_funcs_i915_flip_requestftrace_event_type_funcs_i915_gem_request_wait_beginftrace_event_type_funcs_i915_gem_request_notifyftrace_event_type_funcs_i915_gem_requestftrace_event_type_funcs_i915_gem_ring_flushftrace_event_type_funcs_i915_gem_ring_dispatchftrace_event_type_funcs_i915_gem_ring_sync_toftrace_event_type_funcs_i915_gem_evict_vmftrace_event_type_funcs_i915_gem_evict_everythingftrace_event_type_funcs_i915_gem_evictftrace_event_type_funcs_i915_gem_objectftrace_event_type_funcs_i915_gem_object_faultftrace_event_type_funcs_i915_gem_object_preadftrace_event_type_funcs_i915_gem_object_pwriteftrace_event_type_funcs_i915_gem_object_change_domainftrace_event_type_funcs_i915_page_table_entry_updateftrace_event_type_funcs_i915_page_table_entryftrace_event_type_funcs_i915_vaftrace_event_type_funcs_i915_vma_unbindftrace_event_type_funcs_i915_vma_bindftrace_event_type_funcs_i915_gem_object_createftrace_event_type_funcs_i915_pipe_update_endftrace_event_type_funcs_i915_pipe_update_vblank_evadedftrace_event_type_funcs_i915_pipe_update_startevent_class_switch_mmevent_class_i915_contextevent_class_i915_ppgttevent_class_intel_gpu_freq_changeevent_class_i915_reg_rwevent_class_i915_flip_completeevent_class_i915_flip_requestevent_class_i915_gem_requestevent_class_i915_gem_request_wait_beginevent_class_i915_gem_request_notifyevent_class_i915_gem_ring_flushevent_class_i915_gem_ring_dispatchevent_class_i915_gem_ring_sync_toevent_class_i915_gem_evict_vmevent_class_i915_gem_evict_everythingevent_class_i915_gem_evictevent_class_i915_gem_objectevent_class_i915_gem_object_faultevent_class_i915_gem_object_preadevent_class_i915_gem_object_pwriteevent_class_i915_gem_object_change_domainevent_class_i915_page_table_entry_updateevent_class_i915_page_table_entryevent_class_i915_vaevent_class_i915_vma_unbindevent_class_i915_vma_bindevent_class_i915_gem_object_createevent_class_i915_pipe_update_endevent_class_i915_pipe_update_vblank_evadedevent_class_i915_pipe_update_start__tracepoint_ptr_switch_mm__tpstrtab_switch_mm__tracepoint_ptr_i915_context_free__tpstrtab_i915_context_free__tracepoint_ptr_i915_context_create__tpstrtab_i915_context_create__tracepoint_ptr_i915_ppgtt_release__tpstrtab_i915_ppgtt_release__tracepoint_ptr_i915_ppgtt_create__tpstrtab_i915_ppgtt_create__tracepoint_ptr_intel_gpu_freq_change__tpstrtab_intel_gpu_freq_change__tracepoint_ptr_i915_reg_rw__tpstrtab_i915_reg_rw__tracepoint_ptr_i915_flip_complete__tpstrtab_i915_flip_complete__tracepoint_ptr_i915_flip_request__tpstrtab_i915_flip_request__tracepoint_ptr_i915_gem_request_wait_end__tpstrtab_i915_gem_request_wait_end__tracepoint_ptr_i915_gem_request_wait_begin__tpstrtab_i915_gem_request_wait_begin__tracepoint_ptr_i915_gem_request_complete__tpstrtab_i915_gem_request_complete__tracepoint_ptr_i915_gem_request_retire__tpstrtab_i915_gem_request_retire__tracepoint_ptr_i915_gem_request_notify__tpstrtab_i915_gem_request_notify__tracepoint_ptr_i915_gem_request_add__tpstrtab_i915_gem_request_add__tracepoint_ptr_i915_gem_ring_flush__tpstrtab_i915_gem_ring_flush__tracepoint_ptr_i915_gem_ring_dispatch__tpstrtab_i915_gem_ring_dispatch__tracepoint_ptr_i915_gem_ring_sync_to__tpstrtab_i915_gem_ring_sync_to__tracepoint_ptr_i915_gem_evict_vm__tpstrtab_i915_gem_evict_vm__tracepoint_ptr_i915_gem_evict_everything__tpstrtab_i915_gem_evict_everything__tracepoint_ptr_i915_gem_evict__tpstrtab_i915_gem_evict__tracepoint_ptr_i915_gem_object_destroy__tpstrtab_i915_gem_object_destroy__tracepoint_ptr_i915_gem_object_clflush__tpstrtab_i915_gem_object_clflush__tracepoint_ptr_i915_gem_object_fault__tpstrtab_i915_gem_object_fault__tracepoint_ptr_i915_gem_object_pread__tpstrtab_i915_gem_object_pread__tracepoint_ptr_i915_gem_object_pwrite__tpstrtab_i915_gem_object_pwrite__tracepoint_ptr_i915_gem_object_change_domain__tpstrtab_i915_gem_object_change_domain__tracepoint_ptr_i915_page_table_entry_map__tpstrtab_i915_page_table_entry_map__tracepoint_ptr_i915_page_table_entry_alloc__tpstrtab_i915_page_table_entry_alloc__tracepoint_ptr_i915_va_alloc__tpstrtab_i915_va_alloc__tracepoint_ptr_i915_vma_unbind__tpstrtab_i915_vma_unbind__tracepoint_ptr_i915_vma_bind__tpstrtab_i915_vma_bind__tracepoint_ptr_i915_gem_object_create__tpstrtab_i915_gem_object_create__tracepoint_ptr_i915_pipe_update_end__tpstrtab_i915_pipe_update_end__tracepoint_ptr_i915_pipe_update_vblank_evaded__tpstrtab_i915_pipe_update_vblank_evaded__tracepoint_ptr_i915_pipe_update_start__tpstrtab_i915_pipe_update_startgen8_get_seqnogen8_set_seqnoexeclists_check_remove_requestgen8_logical_ring_put_irqgen8_logical_ring_get_irqgen8_init_common_ring__func__.55138gen8_init_render_ringgen9_init_render_ringintel_lr_context_pin.isra.15kref_get.part.16logical_ring_wait_for_space.isra.19intel_logical_ring_begingen8_emit_bb_startgen8_emit_flush_rendergen8_emit_flushexeclists_ctx_descriptor.isra.25lrc_destroy_wa_ctx_obj.isra.17execlists_update_contextexeclists_context_unqueuegen8_emit_request__func__.54656gen8_init_rcs_context__warned.54758__func__.55420__func__.55501logical_ring_init__key.55276__func__.55061__func__.55087.LC29.LC9ring_write_tailgen6_ring_get_seqnoring_get_seqnoring_set_seqnopc_render_get_seqnopc_render_set_seqnowa_addring_wait_for_spacei9xx_ring_put_irqi9xx_ring_get_irqi8xx_ring_put_irqi8xx_ring_get_irqgen8_ring_put_irqgen8_ring_get_irqgen5_ring_put_irqgen6_ring_put_irqgen5_ring_get_irqgen6_ring_get_irqhsw_vebox_put_irqhsw_vebox_get_irqgen9_init_workarounds.isra.13gen8_emit_pipe_control.part.25gen6_bsd_ring_write_tailstop_ringinit_ring_commonCSWTCH.250__func__.54627render_ring_cleanup__func__.54666init_render_ringintel_init_ring_buffer__key.56645__func__.56608i915_dispatch_execbufferi830_dispatch_execbufferi965_dispatch_execbuffergen6_ring_dispatch_execbuffergen8_ring_dispatch_execbufferhsw_ring_dispatch_execbuffergen2_render_ring_flushi9xx_add_requestgen4_render_ring_flushpc_render_add_requestgen6_signalgen6_ring_syncgen6_render_ring_flushgen7_render_ring_flushgen8_rcs_signalgen8_ring_syncgen6_add_requestbsd_ring_flushgen8_xcs_signalgen6_bsd_ring_flushgen6_ring_flushgen8_render_ring_flushintel_rcs_ctx_init__warned.54676fw_domains_put__intel_uncore_forcewake_get__intel_uncore_forcewake_put__gen6_gt_wait_for_fifog4x_reset_completei915_reset_completeassert_device_not_suspended.isra.11__warned.54562intel_uncore_fw_release_timergen6_gt_check_fifodbg.isra.13fw_domains_put_with_fifohsw_unclaimed_reg_debug.isra.14hsw_unclaimed_reg_detect.isra.15mmio_debug_once.54929__func__.54930__gen6_gt_wait_for_thread_c0.isra.17fw_domain_initgen2_write8gen2_read64gen2_read32gen2_write64gen2_read16gen2_write16gen2_read8gen2_write32gen5_read64gen5_read32gen5_read16gen5_read8gen5_write64gen5_write32gen5_write16gen5_write8vgpu_read64vgpu_write64vgpu_write16vgpu_read32vgpu_read8vgpu_read16vgpu_write32vgpu_write8gen6_write16gen6_write64gen6_write32gen6_write8hsw_write16hsw_write64hsw_write32hsw_write8gen6_read8gen6_read64gen6_read16gen6_read32gen9_read16gen9_read8gen9_read32gen9_read64gen9_write16gen9_shadowed_regsgen9_write32gen9_write8gen9_write64vlv_read32vlv_read16vlv_read8vlv_read64gen8_write8gen8_shadowed_regsgen8_write64gen8_write16gen8_write32chv_read64chv_write16chv_write32chv_write8chv_write64fw_domains_getforcewake_domain_namesfw_domains_get_with_thread_statuschv_read16chv_read32chv_read8__intel_uncore_early_sanitize__func__.55690gen6_null_state_relocsgen6_null_state_batchgen7_null_state_relocsgen7_null_state_batchgen8_null_state_relocsgen8_null_state_batchgen9_null_state_relocsgen9_null_state_batchg4x_audio_codec_disable__func__.54635hsw_audio_codec_disable__func__.54663ilk_audio_codec_disable__func__.54699i915_audio_component_unbindi915_audio_component_bindi915_audio_component_opsi915_audio_component_get_poweri915_audio_component_get_cdclk_freq__warned.54837i915_audio_component_put_poweri915_audio_component_codec_wake_overrideaudio_config_hdmi_pixel_clock.isra.1hdmi_audio_clock__func__.54613hsw_audio_codec_enable__func__.54678ilk_audio_codec_enable__func__.54735g4x_audio_codec_enable__func__.54647__func__.54770i915_audio_component_bind_opsvalidate_vbt__func__.54793fill_detail_timing_dataintel_no_opregion_vbt_callback__func__.54781intel_no_opregion_vbt__func__.54626panel_type__func__.54592__func__.54540__func__.54554__func__.54659__func__.54721__func__.54693__func__.54608__func__.54753__func__.54562__func__.54618__func__.54773__func__.54584__arch_hweight32intel_num_dvo_pipesintel_pipe_set_base_atomicintel_update_pipe_sizeironlake_pfit_enableironlake_pfit_disablevalleyview_calc_cdclki9xx_crtc_offbroadwell_get_display_clock_speedilk_get_display_clock_speedi945_get_display_clock_speedi915_get_display_clock_speedi9xx_misc_get_display_clock_speedi865_get_display_clock_speedi855_get_display_clock_speedi830_get_display_clock_speedintel_cpu_transcoder_set_m_nintel_set_pipe_timingsintel_cpu_transcoder_get_m_nintel_default_queue_flipintel_modeset_update_staged_output_stateibx_pch_dpll_mode_setintel_commit_primary_planeintel_disable_primary_plane__raw_spin_unlock_irqchv_clockpineview_clocki9xx_clockskylake_get_display_clock_speedvlv_clockvlv_update_cdclk__func__.58723cpt_set_fdi_bc_bifurcation__func__.57819clear_intel_crtc_stateassert_planes_disabledassert_sprites_disabledassert_fdi_rxassert_pch_dp_disabledassert_fdi_txi9xx_set_pipeconf__func__.59781intel_crtc_update_cursor__func__.60839__warned.60812intel_disable_cursor_planeintel_commit_cursor_planecompute_m_npage_flip_completedivb_manual_fdi_link_trainsnb_b_fdi_train_param__func__.57678gen6_fdi_link_train__func__.57640pipe_dsl_stoppedibx_pch_dpll_enablevlv_prepare_plllpt_disable_clkout_dpintel_user_framebuffer_create_handleintel_mode_max_pixclkintel_modeset_setup_plane_stateintel_dump_pipe_config__func__.61715__func__.61704do_intel_finish_page_flipcheck_wm_statequirk_invert_brightnessintel_dmi_reverse_brightnessquirk_backlight_presentquirk_ssc_force_disablequirk_pipeb_forcequirk_pipea_forceintel_gen7_queue_flip__warned.61366intel_gen6_queue_flipintel_gen4_queue_flipvalleyview_get_display_clock_speedi915gm_get_display_clock_speedpnv_get_display_clock_speedassert_vblank_disabledhaswell_crtc_compute_clockintel_check_cursor_plane__func__.62747i915_disable_vgaintel_PLL_is_validassert_pch_hdmi_disabledintel_fill_fb_ggtt_viewintel_unpin_fb_obj__warned.57055ironlake_pch_transcoder_set_timings.isra.14hsw_crtc_supports_ips.isra.15haswell_get_display_clock_speedintel_get_pipe_timings.isra.27hsw_read_dcompintel_fuzzy_clock_checkintel_pipe_config_comparecheck_crtc_state__func__.62098intel_pipe_will_have_type.isra.41intel_limitintel_limits_bxtintel_limits_chvintel_limits_vlvintel_limits_i9xx_lvdsintel_limits_i9xx_sdvointel_limits_pineview_lvdsintel_limits_pineview_sdvointel_limits_i8xx_lvdsintel_limits_i8xx_dvointel_limits_i8xx_dacintel_limits_ironlake_dacintel_limits_ironlake_dual_lvds_100mintel_limits_ironlake_dual_lvdsintel_limits_g4x_dual_channel_lvdsintel_limits_g4x_single_channel_lvdsintel_limits_g4x_hdmiintel_limits_ironlake_single_lvds_100mintel_limits_ironlake_single_lvdsintel_limits_g4x_sdvoi9xx_find_best_dpllpnv_find_best_dpllg4x_find_best_dplli9xx_update_pll_dividers.isra.43vlv_PLL_is_optimal.isra.44__warned.55879chv_find_best_dpllvlv_find_best_dpllport_to_power_domain__warned.58501ironlake_get_pfit_config.isra.46i9xx_crtc_clock_get.isra.48__func__.61110assert_pch_transcoder_disabledibx_pch_dpll_disablehaswell_get_pipe_config__func__.60789ibx_pch_dpll_get_hw_statehsw_write_dcompkref_get.part.65__warned.15929intel_gen3_queue_flipintel_gen2_queue_flipupdate_state_fb.isra.73update_scanline_offsetskl_update_scaler_users.part.83__func__.58008ironlake_get_pipe_configlpt_init_pch_refclkassert_plane.constprop.93assert_cursor.constprop.94assert_dsi_pll.constprop.95__intel_pageflip_stall_checki9xx_get_pipe_configchv_prepare_pll.isra.61intel_user_framebuffer_destroyintel_unpin_work_fnintel_crtc_destroyintel_crtc_has_pending_flipcheck_shared_dpll_state__func__.62150intel_disable_pipevalleyview_modeset_global_resources__func__.58777i9xx_get_refclk__func__.59483i9xx_crtc_compute_clockintel_disable_shared_dpll__func__.56754ironlake_crtc_disableintel_enable_shared_dpll__func__.56733intel_enable_pipeironlake_pch_enablechv_enable_pll.isra.77vlv_enable_pll.isra.78chv_disable_pllvlv_disable_pllironlake_fdi_link_train__func__.57613i9xx_pfit_enablei9xx_crtc_disable__func__.59040__warned.56955__func__.56962i9xx_get_initial_plane_config__func__.59911ironlake_get_initial_plane_config__func__.60447__func__.57040__warned.57027intel_crtc_page_flipintel_mmio_flip_work_func__func__.61535i9xx_update_primary_planeironlake_update_primary_plane__func__.57338intel_framebuffer_init__func__.63175intel_fb_funcsintel_alloc_initial_plane_obj.isra.82__func__.57102skylake_get_initial_plane_config__func__.60407__func__.61415__func__.57352__func__.57373__func__.57385__func__.57397skylake_update_primary_plane__warned.57774ironlake_crtc_off__func__.57897ironlake_crtc_compute_clock__func__.60166__func__.60340skylake_pfit_update__func__.58032haswell_crtc_disable__func__.58469intel_post_enable_primaryintel_crtc_enable_planesintel_finish_crtc_commitintel_pre_disable_primaryintel_crtc_disable_planesintel_crtc_load_lutintel_crtc_gamma_setintel_begin_crtc_commit__warned.58512get_crtc_power_domains__intel_set_modebroxton_modeset_global_resources__func__.58625skl_cdclk_frequencies__func__.58684intel_modeset_compute_config__func__.61839__func__.59222__func__.61666__func__.59329__func__.59267i9xx_crtc_enablevalleyview_crtc_enableironlake_crtc_enable__func__.56720haswell_crtc_enable__func__.58386__func__.57801__func__.60058intel_setup_outputs__func__.63043__func__.60656__func__.60662intel_framebuffer_create_for_mode.constprop.92intel_user_framebuffer_create__func__.61179__warned.61496__func__.62042__func__.59155intel_set_modeload_detect_mode__func__.61019__func__.61055intel_crtc_set_config__func__.62402__func__.62378__func__.62324__func__.62504intel_check_primary_plane__func__.63769__func__.63703__func__.63839__func__.63755__func__.63795intel_quirksintel_mode_funcs__compound_literal.0__key.63497skl_primary_formatsintel_cursor_formatsintel_crtc_funcsi8xx_primary_formatsi965_primary_formatsintel_helper_funcs__func__.63617__func__.62841.LC190.LC247i8xx_fbc_enabledg4x_fbc_enabledintel_fbc_nukeilk_fbc_enabledi8xx_fbc_enable__func__.54421g4x_fbc_enable__func__.54439gen7_fbc_enable__func__.54518intel_fbc_work_fni8xx_fbc_disable__func__.54383ilk_fbc_enable__func__.54483g4x_fbc_disableilk_fbc_disable__func__.54489intel_fbc_cancel_work.isra.4__func__.54536__func__.54607__func__.54586intel_mark_fb_busy.isra.0__func__.54391force_audio_namesbroadcast_rgb_namesupdate_polyphase_filtery_static_hcoeffsuv_static_hcoeffscheck_gamma_boundsintel_overlay_map_regs.isra.15intel_overlay_release_old_vid_tailintel_overlay_off_tailintel_overlay_do_wait_requestintel_overlay_release_old_vidintel_overlay_do_put_image__func__.54499intel_overlay_recover_from_interrupt__func__.54814__func__.54854intel_psr_activateintel_psr_exitintel_psr_write_vsc.constprop.3intel_psr_work__func__.54624__func__.54532aux_msg.54424__key.54866vlv_sideband_rw.constprop.1__func__.54392ivb_disable_planeilk_disable_planeintel_commit_sprite_planeintel_check_sprite_plane__func__.54811skl_disable_planevlv_disable_planeskl_update_plane__func__.54521ivb_update_planeilk_update_planevlv_update_planeilk_plane_formatssnb_plane_formatsvlv_plane_formatsskl_plane_formatsintel_dsm_detectintel_dsm_guid__func__.57974intel_dsm_priv__func__.57963CSWTCH.7CSWTCH.9__func__.57986swsci__print_once.57939__func__.57940asle_work__func__.58071__func__.58048__func__.58043__func__.58053__func__.58011__func__.58038__func__.58057__func__.58033__func__.58028__func__.58023intel_opregion_video_eventsystem_opregion__warned.57975power_state_mapintel_opregion_notifierdescriptor.58111CSWTCH.84descriptor.58123__func__.58169__func__.58180__func__.58112intel_crtc_fb_gamma_setintel_crtc_fb_gamma_getintel_fbdev_pan_displayintel_fbdev_blankintel_fbdev_set_parintel_fb_initial_config__func__.55625intelfb_allocintelfb_createintelfb_ops__func__.55567intel_fb_helper_funcs__func__.55668intel_fbdev_suspend_worker__func__.55754ch7017_detectch7017_mode_validch7017_destroych7017_read.isra.0ch7017_dump_regs__func__.54480ch7017_get_hw_statech7017_write.isra.1ch7017_dpmsch7017_mode_set__func__.54466ch7017_init__func__.54444ch7xxx_mode_validch7xxx_readb__func__.54451ch7xxx_dump_regsch7xxx_get_hw_statech7xxx_writeb__func__.54461ch7xxx_detectch7xxx_mode_setch7xxx_destroych7xxx_dpmsch7xxx_initch7xxx_idsch7xxx_dids__func__.54472ivch_detectivch_mode_validivch_read__func__.54427ivch_dump_regs__func__.54482ivch_get_hw_stateivch_write__func__.54437ivch_mode_setivch_destroyivch_dpmsivch_initns2501_detectns2501_destroyns2501_readb__func__.54452ns2501_get_hw_statens2501_writeb__func__.54462ns2501_mode_setns2501_modesmode_agnostic_values__func__.54488ns2501_mode_valid__func__.54478ns2501_dpms__func__.54510ns2501_init__func__.54470sil164_mode_validsil164_mode_setsil164_readb__func__.54423sil164_dump_regssil164_get_hw_statesil164_detectsil164_destroysil164_dpmssil164_init__func__.54441tfp410_mode_validtfp410_mode_settfp410_readbtfp410_dump_regs__func__.54476tfp410_get_hw_statetfp410_detecttfp410_getidtfp410_destroytfp410_dpmstfp410_init__func__.54603__func__.54661__func__.54579intel_plane_atomic_updateintel_plane_atomic_checkkzalloc.constprop.0__func__.54614__func__.54621intel_crt_get_flagsintel_crt_set_dpmsintel_disable_crtpch_disable_crtpch_post_disable_crtintel_enable_crtintel_crt_compute_configintel_crt_set_propertyintel_crt_mode_validintel_crt_reset__func__.55171intel_crt_get_hw_stateintel_crt_get_confighsw_crt_post_disable__func__.54870hsw_crt_pre_enablehsw_crt_get_configintel_crt_destroyintel_crt_dpmsintel_no_crt_dmi_callbackintel_crt_get_edidintel_crt_ddc_get_modesintel_crt_get_modesintel_crt_detect_ddc__func__.55054intel_crt_detect__func__.55113__func__.55030__func__.54948__func__.54970__func__.55080intel_no_crtintel_crt_connector_funcsintel_crt_enc_funcsintel_crt_connector_helper_funcshsw_ddi_pll_disableskl_ddi_pll_disableskl_dpll_regsbroxton_phy_uninitbxt_ddi_pll_disableddi_get_encoder_porthsw_ddi_pll_enablebxt_ddi_pll_get_hw_state__func__.55379__func__.55082bxt_ddi_pll_enableintel_ddi_hot_plugintel_enable_ddiintel_ddi_compute_configintel_ddi_destroyintel_ddi_calc_wrpll_linkintel_ddi_get_crtc_encoderintel_wait_ddi_buf_idleintel_ddi_post_disableskl_ddi_pll_get_hw_statehsw_ddi_pll_get_hw_stateintel_disable_ddiskl_ddi_pll_enablebroxton_phy_init__func__.54552__func__.55475__func__.54941__func__.54915__func__.54829bxt_ddi_translations_dpbxt_ddi_translations_hdmiskl_ddi_translations_hdmiskl_ddi_translations_edpskl_ddi_translations_dphsw_ddi_translations_dphsw_ddi_translations_hdmihsw_ddi_translations_fdibdw_ddi_translations_dpbdw_ddi_translations_hdmibdw_ddi_translations_fdibdw_ddi_translations_edpintel_ddi_pre_enable__func__.55411intel_ddi_funcs__func__.55508intel_hrawclkvlv_pipe_has_pp_onvlv_pipe_has_vdd_onvlv_pipe_anyvlv_initial_pps_pipei9xx_get_aux_clock_dividervlv_get_aux_clock_dividerskl_get_aux_clock_divideri9xx_get_aux_send_ctlskl_get_aux_send_ctlintel_dp_source_supports_hbr2intel_dp_prepare_intel_dp_set_link_trainpps_lockintel_dp_link_down__func__.56709vlv_post_disable_dpilk_get_aux_clock_dividerpps_unlockintel_dp_dpcd_read_wakeintel_dp_set_link_trainintel_dp_set_drrs_state__func__.57211intel_edp_drrs_downclock_workedp_panel_vdd_schedule_offintel_dp_connector_unregisterintel_dp_set_edidintel_dp_forceintel_dp_connector_destroyintel_dp_set_property__func__.57001ilk_post_disable_dpg4x_pre_enable_dp__func__.55580__func__.55816intel_dp_get_config__func__.55929intel_dp_get_hw_state__func__.55878g4x_digital_port_connected.isra.9intel_dp_max_link_bw.isra.10hsw_get_aux_clock_divider_pp_ctrl_reg.part.16vlv_power_sequencer_pipeedp_have_panel_vddintel_edp_panel_vdd_sanitize__func__.57024ironlake_get_pp_controledp_panel_vdd_off_sync_pp_stat_reg.part.15__func__.55709vlv_detach_power_sequencer__func__.56132vlv_steal_power_sequencer__func__.56148intel_dp_init_panel_power_sequencerintel_dp_init_panel_power_sequencer_registersvlv_dpllchv_dpll__func__.54856__func__.54903edp_have_panel_power__func__.57197__func__.57120vlv_initial_power_sequencer_setup__func__.54937edp_notify_handleredp_panel_vdd_workintel_dp_encoder_suspend_intel_edp_backlight_offintel_dp_probe_oui.part.17__func__.56768intel_dp_probe_mst__func__.56780edp_panel_vdd_off.part.22intel_dp_encoder_resetintel_dp_get_modessnprintf_int_array.constprop.30intel_dp_common_ratesskl_ratesdefault_ratesintel_dp_print_rates__func__.55451intel_dp_get_dpcd__func__.56747intel_dp_detect_dpcd__func__.56872intel_dp_detect__func__.56948__func__.56829wait_panel_status__func__.55638wait_panel_power_cycle__func__.55662edp_panel_vdd_on__func__.55687intel_dp_aux_ch__func__.55029__func__.55180intel_dp_aux_transferedp_panel_on__func__.55654__func__.55736intel_dp_set_signal_levelsCSWTCH.355__func__.56595__func__.56513__func__.56484__func__.56525__func__.56497intel_dp_update_link_trainCSWTCH.351CSWTCH.352CSWTCH.353intel_dp_reset_link_train.constprop.29_intel_edp_backlight_onintel_edp_backlight_power__func__.55805intel_edp_backlight_on.part.27__func__.55787vlv_enable_dpvlv_dp_pre_pll_enablechv_post_disable_dpchv_dp_pre_pll_enablegen4_dpllpch_dpll__func__.55523intel_dp_mode_valid__func__.55770__func__.55658__func__.55798__func__.55844intel_disable_dp__func__.56666__func__.56684intel_dp_check_mst_status__func__.56846__func__.57053__func__.56865intel_enable_dp__func__.56111__func__.56164g4x_enable_dpvlv_pre_enable_dpchv_pre_enable_dp__func__.56797port_mapping.57082__func__.57265intel_dp_connector_funcsintel_dp_connector_helper_funcs__key.57314__func__.57362__func__.57321__func__.57424__func__.55261intel_dp_enc_funcs.LC91intel_dp_mst_enc_get_hw_stateintel_dp_mst_set_propertyintel_mst_atomic_best_encoderintel_mst_best_encoderintel_dp_mst_get_hw_stateintel_dp_mst_hotplugintel_dp_mst_connector_destroyintel_dp_mst_get_modesintel_dp_mst_detectintel_dp_add_mst_connectorintel_dp_mst_connector_funcsintel_dp_mst_connector_helper_funcsintel_dp_mst_enc_get_configintel_mst_enable_dp__func__.54737intel_mst_pre_enable_dp__func__.54726intel_mst_post_disable_dp__func__.54700intel_mst_disable_dpintel_dp_mst_compute_configintel_dp_mst_encoder_destroyintel_dp_mst_mode_validintel_dp_destroy_mst_connector__func__.54871mst_cbsintel_dp_mst_enc_funcsintel_dsi_host_attachintel_dsi_host_detachintel_dsi_detectintel_dsi_prepare__func__.55305intel_dsi_connector_destroyintel_dsi_get_configintel_dsi_get_hw_state__func__.55215intel_dsi_pre_pll_enable__func__.55315intel_dsi_compute_config__func__.55073intel_dsi_encoder_destroyintel_dsi_mode_valid__func__.55251intel_dsi_enable_nop__func__.55146intel_dsi_hot_plug__func__.55062intel_dsi_get_modes__func__.55327wait_for_dsi_fifo_emptydpi_send_cmd.constprop.8intel_dsi_pre_enable__func__.55117__func__.55106__func__.55139intel_dsi_pre_disable__func__.55152intel_dsi_post_disable__func__.55181__func__.55203__func__.55164intel_dsi_host_transferintel_dsi_funcsintel_dsi_host_opsintel_dsi_connector_funcsintel_dsi_connector_helper_funcs__func__.55355lfsr_converts__func__.54629__func__.54653__func__.54682generic_exec_sequenceexec_elem__func__.55043seq_namevbt_panel_enablevbt_panel_preparevbt_panel_unpreparevbt_panel_disablevbt_panel_get_modesmipi_exec_gpiogtablemipi_exec_delaymipi_exec_send_packet__func__.55002vbt_panel_funcs__func__.55118intel_dvo_connector_get_hw_stateintel_dvo_get_hw_stateintel_dvo_get_configintel_disable_dvointel_enable_dvointel_dvo_mode_validintel_dvo_pre_enableintel_dvo_get_modesintel_dvo_destroyintel_dvo_detectintel_dvo_dpmsintel_dvo_compute_configintel_dvo_enc_destroyintel_dvo_enc_funcsintel_dvo_devicesintel_dvo_connector_helper_funcsintel_dvo_connector_funcsg4x_infoframe_enabledibx_infoframe_enabledcpt_infoframe_enabledvlv_infoframe_enabledhsw_infoframe_enabledintel_hdmi_preparevlv_enable_hdmiintel_disable_hdmipch_post_disable_hdmiintel_hdmi_pre_enableintel_write_infoframeintel_hdmi_set_avi_infoframeintel_hdmi_set_spd_infoframeintel_hdmi_set_hdmi_infoframeintel_hdmi_get_modesintel_hdmi_set_edidintel_hdmi_force__func__.55225intel_hdmi_destroyintel_hdmi_set_propertyintel_hdmi_detect__func__.55212intel_enable_hdmi__func__.55068intel_hdmi_get_configintel_hdmi_get_hw_statepch_disable_hdmig4x_disable_hdmi__func__.55182g4x_infoframe_index__func__.54676g4x_infoframe_enablecpt_write_infoframeibx_write_infoframeg4x_write_infoframevlv_write_infoframehsw_infoframe_enable__func__.54692hsw_write_infoframe__func__.54702assert_hdmi_port_disabledcpt_set_infoframesibx_set_infoframesg4x_set_infoframeshsw_set_infoframesvlv_set_infoframeschv_hdmi_pre_enableintel_hdmi_mode_validvlv_hdmi_post_disablevlv_hdmi_pre_pll_enablechv_hdmi_post_disablechv_hdmi_pre_pll_enablevlv_hdmi_pre_enableintel_hdmi_connector_funcsintel_hdmi_connector_helper_funcsintel_hdmi_enc_funcsget_clockget_dataset_clockset_datagmbus_funcgmbus_wait_hw_statusgmbus_xfer_readgmbus_wait_idlegmbus_xfer__func__.54690intel_i2c_quirk_set.part.0intel_gpio_post_xfergmbus_pins_sklgmbus_pins_bxtgmbus_pinsgmbus_pins_bdwintel_gpio_pre_xfer__key.54720__key.54721gmbus_algorithm__func__.54755intel_lvds_mode_validintel_lid_notifyintel_no_modeset_on_lidintel_no_modeset_on_lid_dmi_callbackintel_no_lvds_dmi_callbackintel_dual_link_lvds_callbackintel_lvds_get_modesintel_lvds_get_configintel_lvds_get_hw_stateintel_lvds_compute_config__func__.58434intel_pre_enable_lvdsintel_lvds_destroyintel_lvds_detect__func__.58447intel_enable_lvdsintel_lvds_set_property__func__.58490intel_disable_lvdsintel_no_lvds__func__.58589intel_lvds_connector_funcsintel_lvds_enc_funcsintel_lvds_connector_helper_funcsintel_dual_link_lvdscentre_horizontallycentre_verticallybdw_get_backlightpch_get_backlightbxt_get_backlightbdw_set_backlightpch_set_backlightbxt_set_backlightscaleintel_panel_compute_brightnessbxt_setup_backlight_vlv_get_backlightvlv_get_backlightvlv_set_backlightintel_panel_actually_set_backlighti9xx_disable_backlighti965_disable_backlightvlv_disable_backlightpch_disable_backlightbxt_disable_backlighti9xx_enable_backlightget_backlight_min_vbt__func__.54855vlv_setup_backlightpch_setup_backlightbdw_setup_backlighti965_enable_backlight__func__.54778vlv_enable_backlightbdw_enable_backlightbxt_enable_backlight__func__.54798i9xx_get_backlighti9xx_setup_backlighti965_setup_backlighti9xx_set_backlightpch_enable_backlight__func__.54746intel_backlight_device_update_status__func__.54815intel_backlight_device_get_brightness__func__.54604__func__.54719__func__.54806__func__.54964intel_backlight_device_ops__func__.54835pch_disable_sdvointel_sdvo_mode_validintel_sdvo_ddc_proxy_funcintel_sdvo_get_dtd_from_modeintel_sdvo_get_mode_from_dtdintel_sdvo_enc_destroyintel_sdvo_connector_initintel_sdvo_connector_funcsintel_sdvo_connector_helper_funcsintel_sdvo_connector_get_hw_stateintel_sdvo_connector_unregisterintel_sdvo_destroyintel_sdvo_get_analog_edidintel_sdvo_write_sdvox.isra.1intel_sdvo_connector_matches_edid.isra.4__func__.55617intel_sdvo_read_byte.isra.5__func__.55058intel_sdvo_read_responsecmd_status_names__func__.55143intel_sdvo_debug_write.isra.6sdvo_cmd_names__func__.55099intel_sdvo_write_cmd__func__.55115intel_sdvo_ddc_proxy_xferintel_sdvo_enable_hotplugintel_sdvo_get_valueintel_sdvo_get_hw_stateintel_sdvo_create_enhance_property_tv__func__.55882intel_sdvo_create_enhance_property__func__.55892__func__.55905intel_sdvo_get_configCSWTCH.203__func__.55477intel_sdvo_set_valueintel_disable_sdvopch_post_disable_sdvointel_sdvo_set_timingintel_enable_sdvointel_sdvo_set_output_timings_from_modeintel_sdvo_get_preferred_input_modeintel_sdvo_compute_configintel_sdvo_set_propertyintel_sdvo_dpmsintel_sdvo_set_avi_infoframe__func__.55299intel_sdvo_pre_enableintel_sdvo_get_modessdvo_tv_modes__func__.55632__func__.55642__func__.55663intel_sdvo_detect__func__.55626intel_sdvo_connector_allocintel_sdvo_analog_init__func__.55819intel_sdvo_dvi_init__func__.55800intel_sdvo_tv_inittv_format_names__func__.55809intel_sdvo_lvds_init__func__.55828intel_sdvo_ddc_proxyintel_sdvo_enc_funcs__func__.55932__func__.55835__func__.55560intel_tv_get_hw_stateintel_disable_tvintel_tv_get_configintel_tv_mode_lookuptv_modesintel_tv_mode_validintel_tv_compute_configintel_enable_tvintel_tv_pre_enablesdtv_csc_yprpbhdtv_csc_yprpbcomponent_levelsintel_tv_destroyintel_tv_set_propertyintel_tv_get_modesinput_res_tableintel_tv_detect__func__.54954__func__.54934__func__.55040intel_tv_connector_funcsintel_tv_enc_funcsintel_tv_connector_helper_funcsntsc_m_levels_compositentsc_m_levels_svideontsc_m_csc_compositentsc_m_csc_svideofilter_tablentsc_j_levels_compositentsc_j_levels_svideontsc_j_csc_compositentsc_j_csc_svideopal_m_levels_compositepal_m_l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